Patents by Inventor Jader Alves De Lima Filho

Jader Alves De Lima Filho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7994766
    Abstract: A current sensor having a pair of sense transistors is disclosed. The sense transistors sense a current conducted by a power transistor of a voltage regulator. The ratio in size between the power transistor and the sense transistors corresponds to a scaling factor M. Each sense transistor has an associated series connected sense resistor. The two sense resistors are unbalanced and provide a differential voltage based on the sensed current at the sense transistor to a transconductor. The transconductor has heavy emitter degeneration to provide an output current substantially proportional to the current conducted by the primary power transistor, the proportion determined by the scaling factor M and a ratio of the emitter degeneration and sense resistors.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: August 9, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jader Alves De Lima Filho, Wallace A. Pimenta
  • Publication number: 20090295353
    Abstract: A current sensor having a pair of sense transistors is disclosed. The sense transistors sense a current conducted by a power transistor of a voltage regulator. The ratio in size between the power transistor and the sense transistors corresponds to a scaling factor M. Each sense transistor has an associated series connected sense resistor. The two sense resistors are unbalanced and provide a differential voltage based on the sensed current at the sense transistor to a transconductor. The transconductor has heavy emitter degeneration to provide an output current substantially proportional to the current conducted by the primary power transistor, the proportion determined by the scaling factor M and a ratio of the emitter degeneration and sense resistors.
    Type: Application
    Filed: May 30, 2008
    Publication date: December 3, 2009
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Jader Alves De Lima Filho, Wallace A. Pimenta
  • Patent number: 7586367
    Abstract: A current sensor senses the current at a sense transistor and generates an output current that is an accurate proportional representation of the current at the sense transistor. Furthermore, the sensed current is relatively independent of the resistive load of the feedback path at feedback control module to which it is applied. In one embodiment, the feedback control module uses the sensed current in a DC-DC voltage converter to regulate a voltage. The current sensor employs a pair of operational amplifiers to match a voltage at a current electrode of a transistor that generates the output current to a voltage at a current electrode of the sense transistor, such that an effective resistance of the transistor generating the output current is significantly higher than the resistive load of the feedback control module, thereby ensuring that the output current is relatively independent of the resistive load of the feedback control module.
    Type: Grant
    Filed: April 25, 2007
    Date of Patent: September 8, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Jader Alves De Lima Filho
  • Patent number: 7518352
    Abstract: A clamping circuit of a DC/DC regulator includes a reference current generator to generate a reference current. The reference current can be based upon a specified maximum voltage across a bootstrap capacitor of the DC/DC regulator. The clamping circuit also includes a current generator that generates a current based on the voltage across the bootstrap capacitor. The current generated by the current generator is compared to the generated reference current. Based on the comparison, the voltage across the bootstrap capacitor is regulated. By regulating the voltage across the bootstrap capacitor based on current, rather than based directly on the voltage across the capacitor, the design of the clamping circuit is simplified compared to voltage-based implementations.
    Type: Grant
    Filed: May 11, 2007
    Date of Patent: April 14, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jader Alves De Lima Filho, Richard Titov Lara Saez, Wallace Alane Pimenta
  • Patent number: 7486129
    Abstract: A voltage reference includes a first cell configured to receive a first proportional to absolute temperature (PTAT) current and a second cell configured to receive a second PTAT current. The first cell includes a diode-connected stack of insulated-gate field-effect transistors (IGFETs). The diode-connected stack of IGFETs includes a first transistor that is configured to be biased in a triode weak inversion region. The second cell includes a diode-connected stack of IGFETs and a serially coupled resistor. A magnitude of the second PTAT current is based on a drain-to-source voltage of the first transistor and a value of the serially coupled resistor. The voltage reference provides a reference voltage at a reference node of the second cell based on the second PTAT current.
    Type: Grant
    Filed: March 1, 2007
    Date of Patent: February 3, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Stefano Pietri, Jader Alves De Lima Filho, Alfredo Olmos
  • Publication number: 20080278135
    Abstract: A clamping circuit of a DC/DC regulator includes a reference current generator to generate a reference current. The reference current can be based upon a specified maximum voltage across a bootstrap capacitor of the DC/DC regulator. The clamping circuit also includes a current generator that generates a current based on the voltage across the bootstrap capacitor. The current generated by the current generator is compared to the generated reference current. Based on the comparison, the voltage across the bootstrap capacitor is regulated. By regulating the voltage across the bootstrap capacitor based on current, rather than based directly on the voltage across the capacitor, the design of the clamping circuit is simplified compared to voltage-based implementations.
    Type: Application
    Filed: May 11, 2007
    Publication date: November 13, 2008
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Jader Alves De Lima Filho, Richard Titov Lara Saez, Wallace Alane Pimenta
  • Publication number: 20080265850
    Abstract: A current sensor senses the current at a sense transistor and generates an output current that is an accurate proportional representation of the current at the sense transistor. Furthermore, the sensed current is relatively independent of the resistive load of the feedback path at feedback control module to which it is applied. In one embodiment, the feedback control module uses the sensed current in a DC-DC voltage converter to regulate a voltage. The current sensor employs a pair of operational amplifiers to match a voltage at a current electrode of a transistor that generates the output current to a voltage at a current electrode of the sense transistor, such that an effective resistance of the transistor generating the output current is significantly higher than the resistive load of the feedback control module, thereby ensuring that the output current is relatively independent of the resistive load of the feedback control module.
    Type: Application
    Filed: April 25, 2007
    Publication date: October 30, 2008
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventor: Jader Alves De Lima Filho
  • Publication number: 20080218253
    Abstract: A voltage reference includes a first cell configured to receive a first proportional to absolute temperature (PTAT) current and a second cell configured to receive a second PTAT current. The first cell includes a diode-connected stack of insulated-gate field-effect transistors (IGFETs). The diode-connected stack of IGFETs includes a first transistor that is configured to be biased in a triode weak inversion region. The second cell includes a diode-connected stack of IGFETs and a serially coupled resistor. A magnitude of the second PTAT current is based on a drain-to-source voltage of the first transistor and a value of the serially coupled resistor. The voltage reference provides a reference voltage at a reference node of the second cell based on the second PTAT current.
    Type: Application
    Filed: March 1, 2007
    Publication date: September 11, 2008
    Inventors: STEFANO PIETRI, Jader Alves De Lima Filho, Alfredo Olmos