Patents by Inventor Jae-Bok Lee

Jae-Bok Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9005499
    Abstract: Disclosed herein is a method of manufacturing a retainer ring for a chemical mechanical polishing device. Insert pins are coupled to an insert ring member. The insert ring member is thereafter disposed in a mold such that a space is defined around the insert ring member in the mold. Subsequently, molten shell material is injected into the mold to form a shell member. Thereby, the retainer ring is manufactured, having a structure such that the insert ring member is completely covered with the shell member.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: April 14, 2015
    Assignee: Will Be S & T Co., Ltd.
    Inventors: Han-Ju Lee, Min-Gyu Kim, Kwang-Hee Ku, Jae-Bok Lee
  • Publication number: 20140254994
    Abstract: The present invention relates to an optical fiber composite cable. The optical fiber composite cable includes at least one power line to transmit power and an optical cable to monitor a state of the power lines, and the optical cable comprises optical fibers, tubes to accommodate the optical fibers, and a protection member to surround the tubes.
    Type: Application
    Filed: March 4, 2014
    Publication date: September 11, 2014
    Applicant: LS Cable & System Ltd.
    Inventors: Chang-Eun CHO, Chan-Yong PARK, Jae-Bok LEE
  • Publication number: 20140211901
    Abstract: The present invention relates to a nuclear power plant cable including: conductors; at least one or more insulation layers adapted to correspondingly surround the conductors; a sheath adapted to surround the insulation layers; and monitoring means adapted to monitor the states of the insulation layers or the state of the sheath in real time.
    Type: Application
    Filed: January 17, 2014
    Publication date: July 31, 2014
    Applicant: LS Cable & System Ltd.
    Inventors: Jae-Bok Lee, Chan-Yong Park, Hyun-Woong Kim
  • Publication number: 20140042825
    Abstract: The long pulse voltage generating switch according to the present invention comprises a switch control unit for generating a control signal that gradually increases a frequency in a front section of a wave height of a long pulse waveform desired to be simulated and gradually decreases the gradually increased frequency in an end section; and a switch turned on and off by the generated control signal and having a constant turn-on time period while the switch is turned on and off. Therefore, a reference voltage waveform of a long pulse waveform to be simulated can be easily generated, and a long pulse current can be easily generated using the reference voltage waveform.
    Type: Application
    Filed: November 25, 2011
    Publication date: February 13, 2014
    Applicant: Agency for Defense Development
    Inventors: Joon Hyuck Kwon, Eung Jo Kim, Jae Bok Lee, Sug Hun Chang
  • Publication number: 20120319321
    Abstract: Disclosed herein is a method of manufacturing a retainer ring for a chemical mechanical polishing device. Insert pins are coupled to an insert ring member. The insert ring member is thereafter disposed in a mold such that a space is defined around the insert ring member in the mold. Subsequently, molten shell material is injected into the mold to form a shell member. Thereby, the retainer ring is manufactured, having a structure such that the insert ring member is completely covered with the shell member.
    Type: Application
    Filed: February 22, 2011
    Publication date: December 20, 2012
    Applicant: Will Be S & T Co., Ltd.
    Inventors: Han-Ju Lee, Min-Gyu Kim, Kwang-Hee Ku, Jae-Bok Lee
  • Patent number: 8335214
    Abstract: Provided are an interface system and a method of controlling the interface system. The interface system may include a memory, a first processor, a second processor, and an interface unit. The memory may be configured to store received data in packets. The first processor may be configured to analyze a header of each of the packets to obtain analysis information. The second processor may be configured to receive and process a payload of the packet that includes the analyzed header and the payload. The interface unit may be configured to transmit only the payload to the second processor based on the analysis information. Since the interface system and the method may directly transmit only the payload of the packet to the processor without copying the payload to a separate memory, memory usage efficiency and system performance may be improved and power consumption may be reduced.
    Type: Grant
    Filed: March 10, 2009
    Date of Patent: December 18, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-bok Lee, Ki-cheol Lee, Yong Ho Song, Jaehyeong Jeong
  • Publication number: 20110202273
    Abstract: A navigation system compresses original map data to generate compressed map data. The navigation system compares a size of the original map data with a size of the compressed map data and selectively transmits the original map data or the compressed map data based on the comparison.
    Type: Application
    Filed: December 2, 2010
    Publication date: August 18, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Igor NOGTEV, Jeong Hwan AHN, Min Su AHN, Ki Cheol LEE, Jae Bok LEE
  • Patent number: 7999258
    Abstract: A display substrate includes a base substrate, a first metal pattern, a second metal pattern, a first transparent conductive layer and a second transparent conductive layer. The first metal pattern is formed on the base substrate, and includes a gate line and a gate electrode connected to the gate line. The second metal pattern includes a data line crossing the gate line, a source electrode connected to the data line and a drain electrode being spaced apart from the source electrode. The first transparent conductive layer includes a capping layer capping the second metal pattern and a common electrode formed in a pixel area. The second transparent conductive layer includes a pixel electrode having a plurality of openings, contacting the capping layer capping the drain electrode, and facing the common electrode.
    Type: Grant
    Filed: March 27, 2008
    Date of Patent: August 16, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Bok Lee, Chun-Gi You, Sang-Hyun Jun
  • Patent number: 7858450
    Abstract: An optic mask for crystallizing amorphous silicon comprises a first slit region including a plurality of slits regularly arranged for defining incident region of laser beam, wherein the slits of the first slit region are formed to slope by a predetermined angle to the direction of transfer of the optic mask in crystallization process, and wherein the slits of the first slit region includes a first slit having a first length and a second slit having a second length which is longer than the first length.
    Type: Grant
    Filed: January 5, 2005
    Date of Patent: December 28, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ui-Jin Chung, Myung-Koo Kang, Jae-Bok Lee
  • Publication number: 20100176401
    Abstract: An X-ray detector includes a gate wire formed on a substrate, the gate wire including a gate line, a gate electrode, and a gate pad, a gate insulating layer formed on the gate wire, a data wire formed on the gate insulating layer, the data wire including a data line intersecting the gate line, a source electrode, a drain electrode, and a data pad, a lower storage electrode formed on the gate insulating layer, the lower storage electrode comprising an opaque conductor material, and an upper storage electrode formed on the lower storage electrode, the upper storage electrode connected to the source electrode.
    Type: Application
    Filed: January 6, 2010
    Publication date: July 15, 2010
    Inventors: JAE-BOK LEE, Young-Bae Jung
  • Publication number: 20090238186
    Abstract: Provided are an interface system and a method of controlling the interface system. The interface system may include a memory, a first processor, a second processor, and an interface unit. The memory may be configured to store received data in packets. The first processor may be configured to analyze a header of each of the packets to obtain analysis information. The second processor may be configured to receive and process a payload of the packet that includes the analyzed header and the payload. The interface unit may be configured to transmit only the payload to the second processor based on the analysis information. Since the interface system and the method may directly transmit only the payload of the packet to the processor without copying the payload to a separate memory, memory usage efficiency and system performance may be improved and power consumption may be reduced.
    Type: Application
    Filed: March 10, 2009
    Publication date: September 24, 2009
    Inventors: Jae-bok Lee, Ki-cheol Lee, Yong Ho Song, Jaehyeong Jeong
  • Publication number: 20090020758
    Abstract: A display substrate includes a base substrate, a first metal pattern, a second metal pattern, a first transparent conductive layer and a second transparent conductive layer. The first metal pattern is formed on the base substrate, and includes a gate line and a gate electrode connected to the gate line. The second metal pattern includes a data line crossing the gate line, a source electrode connected to the data line and a drain electrode being spaced apart from the source electrode. The first transparent conductive layer includes a capping layer capping the second metal pattern and a common electrode formed in a pixel area. The second transparent conductive layer includes a pixel electrode having a plurality of openings, contacting the capping layer capping the drain electrode, and facing the common electrode.
    Type: Application
    Filed: March 27, 2008
    Publication date: January 22, 2009
    Inventors: Jae-Bok Lee, Chun-Gi You, Sang-Hyun Jun
  • Publication number: 20080074137
    Abstract: A display substrate includes a signal line, a test switch, a test pad, and a first electrostatic dispersion line. The signal line is formed in the display area of a base substrate. The test switch is formed in a peripheral area of the base substrate surrounding the display area. The test switch applies a test signal to the signal line. The test pad is electrically connected to the test switch and receives the test signal The first electrostatic dispersion line is extended from the test pad to an end of the base substrate.
    Type: Application
    Filed: September 20, 2007
    Publication date: March 27, 2008
    Inventors: Hyun-Young Kim, Chun-Gi You, Jae-Bok Lee, Kwan-Wook Jung, Hyung-Don Na, Seung-Gyu Tae, Jung-Yun Kim
  • Publication number: 20050173752
    Abstract: An optic mask for crystallizing amorphous silicon comprises a first slit region including a plurality of slits regularly arranged for defining incident region of laser beam, wherein the slits of the first slit region are formed to slope by a predetermined angle to the direction of transfer of the optic mask in crystallization process, and wherein the slits of the first slit region includes a first slit having a first length and a second slit having a second length which is longer than the first length.
    Type: Application
    Filed: January 5, 2005
    Publication date: August 11, 2005
    Inventors: Ui-Jin Chung, Myung-Koo Kang, Jae-Bok Lee