Patents by Inventor Jae-Cheol Yoo

Jae-Cheol Yoo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7709340
    Abstract: A semiconductor integrated circuit device may include a semiconductor substrate, a static memory cell on the semiconductor substrate, a tensile stress film on the pull-down transistors, and a compressive stress film on the pass transistors. The static memory cell may include multiple pull-up transistors and pull-down transistors, which form a latch, and multiple pass transistors may be used to access the latch.
    Type: Grant
    Filed: February 12, 2007
    Date of Patent: May 4, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-hyon Ahn, Jae-cheol Yoo, Ki-seog Youn, Kwan-jong Roh, Su-gon Bae, Ki-young Kim
  • Publication number: 20070187770
    Abstract: A semiconductor integrated circuit device may include a semiconductor substrate, a static memory cell on the semiconductor substrate, a tensile stress film on the pull-down transistors, and a compressive stress film on the pass transistors. The static memory cell may include multiple pull-up transistors and pull-down transistors, which form a latch, and multiple pass transistors may be used to access the latch.
    Type: Application
    Filed: February 12, 2007
    Publication date: August 16, 2007
    Inventors: Jong-hyon Ahn, Jae-cheol Yoo, Ki-seog Youn, Kwan-jong Roh, Su-gon Bae, Ki-young Kim
  • Patent number: 6552438
    Abstract: Bonding pads for integrated circuits include first and second spaced apart conductive layers, a third continuous conductive layer between the first and second spaced apart and an array of unaligned spaced apart insulating islands in the third continuous conductive layer and extending therethrough such that sidewalls of the array of insulating islands are surrounded by the third continuous conductive layer, rows of unaligned spaced apart insulating islands. The array can include rows of unaligned spaced apart insulating islands and columns of unaligned spaced apart insulating islands. The array of unaligned spaced apart insulating islands can also include a first insulating island having a first edge in a first direction and a second insulating island, adjacent to the first insulating island in the first direction having a second edge in the first direction that is unaligned with first edge.
    Type: Grant
    Filed: December 21, 2000
    Date of Patent: April 22, 2003
    Assignee: Samsung Electronics Co.
    Inventors: Soo-cheol Lee, Jong-hyon Ahn, Kyoung-mok Son, Heon-jong Shin, Hyae-ryoung Lee, Young-pill Kim, Moo-jin Jung, Son-jong Wang, Jae-Cheol Yoo
  • Publication number: 20010000928
    Abstract: Bonding pads for integrated circuits include first and second spaced apart conductive layers, a third continuous conductive layer between the first and second spaced apart and an array of unaligned spaced apart insulating islands in the third continuous conductive layer and extending therethrough such that sidewalls of the array of insulating islands are surrounded by the third continuous conductive layer, rows of unaligned spaced apart insulating islands. The array can include rows of unaligned spaced apart insulating islands and columns of unaligned spaced apart insulating islands. The array of unaligned spaced apart insulating islands can also include a first insulating island having a first edge in a first direction and a second insulating island, adjacent to the first insulating island in the first direction having a second edge in the first direction that is unaligned with first edge.
    Type: Application
    Filed: December 21, 2000
    Publication date: May 10, 2001
    Inventors: Soo-Cheol Lee, Jong-Hyon Ahn, Kyoung-Mok Son, Heon-Jong Shin, Hyae-Ryoung Lee, Young-Pill Kim, Moo-Jin Jung, Son-Jong Wang, Jae-Cheol Yoo