Abstract: A wiring structure includes a first insulation layer located on a substrate, and first and second plugs located on the substrate and extending through the first insulation layer. The first plug includes an upper peripheral portion that defines a recess and the second plug is adjacent to the first plug. A second insulation layer is located on the first insulation layer, the first plug and the second plug. A bit line structure is located on the second insulation layer and is electrically connected to the first plug. A protection spacer is located on the recess of the first plug and a sidewall of an opening in the second insulation layer. The opening exposes the recess of the first plug, the second plug and the sidewall of the bit line structure. A pad is located in the opening and contacts the second plug.

Abstract: A wiring structure includes a first insulation layer located on a substrate, and first and second plugs located on the substrate and extending through the first insulation layer. The first plug includes an upper peripheral portion that defines a recess and the second plug is adjacent to the first plug. A second insulation layer is located on the first insulation layer, the first plug and the second plug. A bit line structure is located on the second insulation layer and is electrically connected to the first plug. A protection spacer is located on the recess of the first plug and a sidewall of an opening in the second insulation layer. The opening exposes the recess of the first plug, the second plug and the sidewall of the bit line structure. A pad is located in the opening and contacts the second plug.

Abstract: A metal oxide semiconductor (MOS) transistor having a recessed gate electrode and a fabrication method thereof are provided. The MOS transistor includes a semiconductor substrate and an isolation layer formed in a predetermined region of the semiconductor substrate to define an active region. A channel trench region is disposed within the active region to cross the active region. A gate insulating layer is disposed to cover sidewalls and a bottom of the channel trench region. The MOS transistor has a gate pattern that fills the channel trench region and crosses above the active region. A portion of the sidewall of the gate pattern is recessed at an upper corner of the channel trench region and has a width smaller than the width of the top of the gate pattern and smaller than the width of the channel trench region.

Abstract: A recess gate-type semiconductor device includes a gate electrode having a recessed portion at least partially covering a recess trench in an active region, and source/drain regions disposed in the active region that are separated by the gate electrode. The recess trench is separated from sidewalls of a device isolation region in a first direction and contacts sidewalls of the device isolation region in a second direction. The width of the recess trench of the active region in the second direction may be greater than the width of the source/drain regions in the second direction, and the recessed portion of the gate electrode may have tabs protruding in the first direction at its corners. Therefore, the semiconductor device has excellent junction leakage current and excellent refresh characteristics.

Abstract: A recess gate-type semiconductor device includes a gate electrode having a recessed portion at least partially covering a recess trench in an active region, and source/drain regions disposed in the active region that are separated by the gate electrode. The recess trench is separated from sidewalls of a device isolation region in a first direction and contacts sidewalls of the device isolation region in a second direction. The width of the recess trench of the active region in the second direction may be greater than the width of the source/drain regions in the second direction, and the recessed portion of the gate electrode may have tabs protruding in the first direction at its corners. Therefore, the semiconductor device has excellent junction leakage current and excellent refresh characteristics.

Abstract: A metal oxide semiconductor (MOS) transistor having a recessed gate electrode and a fabrication method thereof are provided. The MOS transistor includes a semiconductor substrate and an isolation layer formed in a predetermined region of the semiconductor substrate to define an active region. A channel trench region is disposed within the active region to cross the active region. A gate insulating layer is disposed to cover sidewalls and a bottom of the channel trench region. The MOS transistor has a gate pattern that fills the channel trench region and crosses above the active region. A portion of the sidewall of the gate pattern is recessed at an upper corner of the channel trench region and has a width smaller than the width of the top of the gate pattern and smaller than the width of the channel trench region.