Abstract: The present technology relates to a memory device. A memory device according to the present technology may include a plurality of planes, individual operation controllers configured to respectively control read operations on the plurality of planes, a common operation controller configured to control a program operation or an erase operation on any one of the plurality of planes, a command decoder configured to provide a read command among the plurality of commands to an individual operation controller that controls a plane that is indicated by an address that corresponds to the read command among the individual operation controllers, and configured to provide a program command or an erase command among the plurality of commands to the common operation controller, and a peripheral circuit configured to generate operation voltages that are used for the read operations, the program operation, and the erase operation.

Abstract: A light source module including: a printed circuit board; a light emitting device mounted on the printed circuit board and including a plurality of subarrays each of the plurality of subarrays including a plurality of light emitting cells; and a plurality of driving chips mounted on the printed circuit board, wherein each of the plurality of driving chips respectively drives a corresponding one of the plurality of subarrays, wherein the plurality of subarrays are electrically isolated from each other.

Abstract: According to the present technology, a memory device may include memory cells configured to be programmed so that each of the memory cells has a threshold voltage corresponding to any one of a plurality of program states, a peripheral circuit configured to perform a read operation or a program operation on the memory cells, and control logic configured to control the peripheral circuit to perform a test read operation of reading the memory cells using a test read voltage that is any one read voltage among preset default read voltages, and perform a refresh program operation of applying a refresh program voltage to some memory cells among the memory cells according to the number of memory cells having a threshold voltage greater than the test read voltage.

Abstract: A semiconductor light-emitting device includes a plurality of light-emitting device structures separated from each other and arranged in a matrix form. A pad region at least partially surrounds the plurality of light-emitting device structures. The pad region is disposed outside of the plurality of light-emitting device structures. A partition structure is disposed on a first surface of the plurality of light-emitting device structures and is further disposed between adjacent light-emitting device structures of the plurality of light-emitting device structures. The partition structure defines a plurality of pixel spaces within the plurality of light-emitting device structures. A fluorescent layer is disposed on the first surface of the plurality of light-emitting device structures and fills each of the plurality of pixel spaces.

Abstract: The present technology relates to an electronic device. A memory system for increasing reliability of data includes a memory device including a plurality of pages, and a memory controller configured to correct an error in read data obtained by reading a selected page among the plurality of pages, and determine whether to perform a refresh operation on the selected page based on a number of error bits included in the read data. The memory controller comprises a normal read operation controller configured to control a read operation on the selected page and determine the number of error bits in the read data, an error correction performance component configured to correct the read data, and a data recovery controller configured to control the refresh operation on the selected page based on the number of error bits in the read data when the error in the read data is corrected.

Abstract: In one example, a semiconductor structure comprises a redistribution structure comprising a conductive structure, a cavity substrate on a top side of the redistribution structure and having a cavity and a pillar contacting the redistribution structure, an electronic component on the top surface of the redistribution structure and in the cavity, wherein the electronic component is electrically coupled with the conductive structure, and an encapsulant in the cavity and on the top side of the redistribution structure, contacting a lateral side of the electronic component, a lateral side of the cavity, and a lateral side of the pillar. Other examples and related methods are also disclosed herein.

Abstract: Provided is a system for recognizing a user hand gesture and providing virtual reality content based on deep learning using transfer learning. The system includes a head mounted display (HMD) configured to display, to a user, virtual reality content based on a hand gesture, a hand gesture sensor configured to acquire hand data of the user, and a controller device configured to receive the hand data and convert the received hand data into hand gesture data, manage a hand gesture recognizer on the basis of deep learning, and perform content execution management.

Abstract: A lighting device disclosed in an embodiment of the invention includes a substrate; a light source including a plurality of light emitting devices disposed on the substrate; a resin layer disposed on the substrate; and a first diffusion layer disposed on the resin layer, wherein the resin layer includes a first resin portion disposed on the light source, and a second resin portion adjacent to the first resin portion and disposed on the substrate. The upper surface of the first resin portion has an inclination and is spaced apart from the first diffusion layer, the second resin portion includes a material different from that of the first resin portion, and the second resin portion based on the upper surface of the substrate. The height of the upper surface may be greater than the lowermost height of the upper surface of the first resin portion.

Abstract: A light emitting device is provided. The light emitting device includes a first semiconductor layer; a second semiconductor layer provided on a bottom surface of the first semiconductor layer; an active layer interposed between the first semiconductor layer and the second semiconductor layer; a dielectric layer provided on a bottom surface of the second semiconductor layer; a plurality of first n-contacts provided on a first etched surface of the first semiconductor layer; and a plurality of first p-contacts and a plurality of second p-contacts provided on the bottom surface of the second semiconductor layer. One first n-contact is disposed along a first edge region of the first semiconductor layer, one first p-contact is closer to the one first n-contact than one second p-contact, and an area of the one first p-contact is greater than an area of each of the second p-contacts.

Abstract: A sub-sampling phase-locked loop includes a first phase output unit sub-sampling an output clock of a digitally-controlled oscillator and outputting a sign bit corresponding to a voltage-domain phase and a second phase output unit outputting a gain bit corresponding to a time-domain phase based on a pulse width set according to the output clock and a threshold time set according to the reference clock.

Abstract: Provided are a laser element and a method for manufacturing the same, in which the laser element includes a first clad layer, an optical waveguide disposed on the first clad layer, a second clad layer disposed on the optical waveguide, a first electrode disposed on the second clad layer, and a dummy clad disposed on the optical waveguide and apart from the second clad layer and the first electrode.

Abstract: A sub-sampling phase-locked loop includes a first phase output unit sub-sampling an output clock of a digitally-controlled oscillator and outputting a sign bit corresponding to a voltage-domain phase and a second phase output unit outputting a gain bit corresponding to a time-domain phase based on a pulse width set according to the output clock and a threshold time set according to the reference clock.

Abstract: A display device includes a display panel including a first area and a second area, a first end of the display panel being in the first area and a second end of the display panel being in the second area, wherein the second area extends away from the first area in a first direction, and the second end of the display panel protrudes from the first end of the display panel 1 in a second direction perpendicular to the first direction. a polarizing plate on the display panel, a first end of the polarizing plate being located in the first area overlapping the first end of the display panel in a plan view and an organic layer on the display panel in the second area, the organic layer extending away from the polarizing plate in the second direction, an end of the organic layer overlapping the second end of the display panel in a plan view.

Abstract: A foldable display device includes: a flexible display module including a bendable area having a folding axis and substantially planar members respectively located at opposite sides of the bendable area; and a support disposed on the flexible display module and including a hinge portion and support members, each of the support members being rotatably supported by one of opposite sides of the hinge portion, wherein at least a portion of the folding axis overlaps at least one of the support members in a plan view.

Abstract: A memory system is provided to include a first virtual function controller in communication with a first virtual machine of a host and configured to receive, from the first virtual machine, a command for accessing a namespace and provide, to the first virtual machine, a response to the command; a second virtual function controller in communication with a second virtual machine of the host and configured to be coupled to the namespace and receive the command from the first virtual function controller based on status information of the first virtual function controller and the second virtual function controller; a buffer memory configured to provide an area for data corresponding to the command; and a memory controller configured to access the namespace based on the command and provide the buffer memory with the data.

Abstract: The present technology includes a voltage generator and a memory device including the voltage generator. The voltage generator includes an operation code determiner configured to output a clock control code including the number of planes in response to an operation code, a clock group configured to simultaneously generate clocks having different periods according to the clock control code, and a pump group configured to perform a pumping operation according to the clocks and output operation voltages.

Abstract: In non-limiting examples of the present disclosure, systems, methods and devices for filtering notifications are provided. A notification may be received. A current focus state of a user may be determined. An application priority score for the application that generated the notification may be determined. A notification priority score for the notification may be determined. The notification priority score may be determined based on a contact importance score and/or a content importance score. A combined priority score may be determined from the application priority score and the notification priority score. The notification may be surfaced if the combined priority score meets a threshold surfacing value. The notification may be blocked if the combined priority score does not meet the threshold surfacing value.

Abstract: An etching composition may include a peracetic acid mixture, a fluorine compound, an organic solvent (e.g., acetate-series organic solvent), and water. The etching composition may be used to selectively etch silicon-germanium (SiGe).

Abstract: The present disclosure relate to a semiconductor light emitting device and a method for manufacturing the same. The semiconductor light emitting device comprises a semiconductor light emitting chip, and first electrodes electrically connected to the semiconductor light emitting chip, with the first electrodes each having a planar area larger than that of the semiconductor light emitting chip, wherein lower surfaces of the first electrodes are exposed externally, and an insulating material is filled in-between inner lateral surfaces of the first electrodes.

Abstract: The present technology includes a voltage generator and a memory device including the voltage generator. The voltage generator includes an operation code determiner configured to output a clock control code including the number of planes in response to an operation code, a clock group configured to simultaneously generate clocks having different periods according to the clock control code, and a pump group configured to perform a pumping operation according to the clocks and output operation voltages.