Abstract: A method for monitoring an object is provided. The method includes the steps of: in response to information on a behavior of a domestic animal being estimated from sensor data measured by a sensor for the domestic animal using a machine learning-based behavior recognition model, estimating health status of the domestic animal with reference to the information on the behavior of the domestic animal and a health criterion for the domestic animal; and determining first breeding information on the domestic animal to be provided to a user on the basis of the health status.

Abstract: A method for monitoring an object is provided. The method includes the steps of: in response to information on a behavior of a domestic animal being estimated from sensor data measured by a sensor for the domestic animal using a machine learning-based behavior recognition model, estimating health status of the domestic animal with reference to the information on the behavior of the domestic animal and a health criterion for the domestic animal; and determining first breeding information on the domestic animal to be provided to a user on the basis of the health status.

Abstract: According to one aspect of the present invention, provided is a method for monitoring an object, the method comprising the steps of: in sensor data measured by a sensor for at least one object, specifying pattern data about an unidentified behavior of the at least one object that is not recognized by a machine learning-based behavior recognition model; and determining at least a portion of the pattern data as target data on the basis of at least one of a measurement frequency and a measurement size of the pattern data, and providing information about the target data to a user.

Abstract: A method for managing biometric information is provided. The method includes the steps of: determining whether a cardiac disorder event has occurred to a user on the basis of biometric information measured from the user's body and situation information associated with the biometric information; providing alarm information associated with the cardiac disorder event to the user in response to determining that the cardiac disorder event has occurred; and associating a time point of occurrence of the cardiac disorder event with feedback information acquired from the user in response to the provided alarm information.

Abstract: A method for managing biometric information is provided. The method includes the steps of: determining whether a cardiac disorder event has occurred to a user on the basis of biometric information measured from the user's body and situation information associated with the biometric information; providing alarm information associated with the cardiac disorder event to the user in response to determining that the cardiac disorder event has occurred; and associating a time point of occurrence of the cardiac disorder event with feedback information acquired from the user in response to the provided alarm information.

Abstract: Provided is a battery cell having a structure in which outer circumferential sides of a cell case are sealed by heat fusion in a state in which an electrode assembly including a cathode, an anode, and a separator is housed in a cell case together with an electrolyte solution, wherein the electrode assembly and the cell case have a structure in which both ends at positions opposite to each other are together curved in the same direction so that a curved surface is formed on an outer surface of the battery cell, and at least one of the heat-fused outer circumferential sides of the cell case is curved to adhere to a curved surface while forming an inner surface.

Abstract: A memory cell structure of a metal (or via) programmable ROM whereby a transistor is shared between bit cells of the programmable ROM. Such a memory cell structure may include: a word line; a bit line; first and second virtual grounding lines; a grounding line; a first bit cell selected by signals of the word line and the first virtual grounding line; and a second bit cell selected by signals of the word line and the second virtual grounding line, wherein a cell transistor, one side of which is connected to the bit line is shared both by the first and second bit cells. Also, the other side of the cell transistor may be floated or connected to the bit line or, alternatively, connected to any one of the first virtual grounding line, the second virtual grounding line and the grounding line, and the gate of the cell transistor is connected to the word line.

Abstract: A high-speed programmable ROM, a memory cell structure therefor, and a method for writing data on/reading data from the programmable ROM are provided.

Abstract: A device and method for testing memory access times of a memory using a phase-locked loop (PLL) are described. The device for testing the memory access time of a memory may include a PLL and a test unit, and may also include a memory controller. The PLL may generate a test signal having a variable period. The test unit may compare the test signal with a memory output and may output the result of the comparison as a test result for the memory access time. The test unit may include a delay portion and a test portion. The delay portion may delay the test signal to generate first to n-th (n may be a natural number) sub-test signals. The test portion may compare the first to n-th sub-test signals with the memory output.

Abstract: A memory cell structure of a metal (or via) programmable ROM whereby a transistor is shared between bit cells of the programmable ROM. Such a memory cell structure may include: a word line; a bit line; first and second virtual grounding lines; a grounding line; a first bit cell selected by signals of the word line and the first virtual grounding line; and a second bit cell selected by signals of the word line and the second virtual grounding line, wherein a cell transistor, one side of which is connected to the bit line is shared both by the first and second bit cells. Also, the other side of the cell transistor may be floated or connected to the bit line or, alternatively, connected to any one of the first virtual grounding line, the second virtual grounding line and the grounding line, and the gate of the cell transistor is connected to the word line.

Abstract: A memory cell structure of a metal (or via) programmable ROM whereby a transistor is shared between bit cells of the programmable ROM. Such a memory cell structure may include: a word line; a bit line; first and second virtual grounding lines; a grounding line; a first bit cell selected by signals of the word line and the first virtual grounding line; and a second bit cell selected by signals of the word line and the second virtual grounding line, wherein a cell transistor, one side of which is connected to the bit line is shared both by the first and second bit cells. Also, the other side of the cell transistor may be floated or connected to the bit line or, alternatively, connected to any one of the first virtual grounding line, the second virtual grounding line and the grounding line, and the gate of the cell transistor is connected to the word line.

Abstract: Read only memory(ROM) integrated circuit devices include a ROM cell block. A plurality of virtual ground lines and bit lines are coupled to the ROM cell block. A precharge circuit, including a virtual ground line precharge controller, virtual ground line precharging unit, bit line precharge controller and bit line precharging unit, independently controls timing of precharging the virtual ground lines and the bit lines. The precharge circuit may be configured to deactivate precharging of the virtual ground lines before deactivating precharging of the bit lines. Precharging of the virtual ground lines may be deactivated substantially concurrently with activation of discharging of the virtual ground lines.

Abstract: The present invention relates to a method for reducing auto-fluorescence signals from a sample tissue in confocal Raman microscopy and to a method for diagnosing skin cancers using the same method. Raman spectroscopy has strong potential for providing non-invasive diagnosis of skin cancer. Auto-fluorescence signals from tissues, which interfere with the Raman signals, were greatly reduced using a confocal slit adjustment. Distinct Raman band differences between normal and BCC tissues for the amide I mode, the amide III mode and the PO2? symmetric stretching mode, showed that the present invention has strong potential for use as a dermatological diagnostic tool without the need for statistical treatment of spectral data. It was also possible to precisely differentiate BCC tissue from surrounding non-cancerous tissue using the confocal Raman depth profiling technique.

Abstract: A high-speed programmable ROM, a memory cell structure therefor, and a method for writing data on/reading data from the programmable ROM are provided.

Abstract: Read only memory(ROM) integrated circuit devices include a ROM cell block. A plurality of virtual ground lines and bit lines are coupled to the ROM cell block. A precharge circuit, including a virtual ground line precharge controller, virtual ground line precharging unit, bit line precharge controller and bit line precharging unit, independently controls timing of precharging the virtual ground lines and the bit lines. The precharge circuit may be configured to deactivate precharging of the virtual ground lines before deactivating precharging of the bit lines. Precharging of the virtual ground lines may be deactivated substantially concurrently with activation of discharging of the virtual ground lines.

Abstract: A high speed programmable ROM, a memory cell structure therefor, and a method for writing data on/reading data from the programmable ROM are provided.

Abstract: A memory cell structure of a metal (or via) programmable ROM whereby a transistor is shared between bit cells of the programmable ROM. Such a memory cell structure may include: a word line; a bit line; first and second virtual grounding lines; a grounding line; a first bit cell selected by signals of the word line and the first virtual grounding line; and a second bit cell selected by signals of the word line and the second virtual grounding line, wherein a cell transistor, one side of which is connected to the bit line is shared both by the first and second bit cells. Also, the other side of the cell transistor may be floated or connected to the bit line or, alternatively, connected to any one of the first virtual grounding line, the second virtual grounding line and the grounding line, and the gate of the cell transistor is connected to the word line.

Abstract: A read only memory (ROM) cell, a method for programming a ROM cell, a method for forming a layout of a ROM cell, and a ROM device including ROM cells are disclosed. The ROM cell includes a gate connected to a word line, a drain (or a source) connected to a bit line, and a source (or a drain) connected to a ground voltage line, a first selection signal line or a second selection signal line, or having no connection with the first and second selection signal lines, wherein the ROM cell is programmed with data “00” by connecting the source (or the drain) to the ground voltage line, with data “10” by connecting the source (or the drain) to the first selection signal line, with data “01” by connecting the source (or the drain) to the second seletion signal line and data “11” by not connecting the source (or the drain) to any signal lines.

Abstract: Read only memory (ROM) integrated circuit devices include one or more storage cells. A virtual ground line and a bit line are coupled to the storage cell. A precharge circuit independently controls timing of precharging of the virtual ground line and the bit line. The precharge circuit may be configured to deactivate precharging of the virtual ground line before deactivating precharging of the bit line. Precharging of the virtual ground line may be deactivated substantially concurrently with activation of discharging of the virtual ground line. Methods of operating such ROM integrated circuit devices are also provided.

Abstract: A memory cell structure of a metal (or via) programmable ROM whereby a transistor is shared between bit cells of the programmable ROM. Such a memory cell structure may include: a word line; a bit line; first and second virtual grounding lines; a grounding line; a first bit cell selected by signals of the word line and the first virtual grounding line; and a second bit cell selected by signals of the word line and the second virtual grounding line, wherein a cell transistor, one side of which is connected to the bit line is shared both by the first and second bit cells. Also, the other side of the cell transistor may be floated or connected to the bit line or, alternatively, connected to any one of the first virtual grounding line, the second virtual grounding line and the grounding line, and the gate of the cell transistor is connected to the word line.