Patents by Inventor Jae Choon Cho

Jae Choon Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070264755
    Abstract: Disclosed is a method of manufacturing a printed circuit board for fine circuit formation, in which an unnecessary metal layer formed on the upper portion of a circuit pattern is removed through mechanical polishing and then chemical etching. In place of expensive chemical mechanical polishing, in the method of the invention, mechanical polishing and chemical etching are continuously applied to thus sequentially remove and planarize the unnecessary metal layer. Thereby, through an inexpensive, simple, and continuous process, the planarization procedure can be precisely performed, thus making it possible to apply the method to large areas and economically realize a fine circuit pattern.
    Type: Application
    Filed: March 27, 2007
    Publication date: November 15, 2007
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Choon Keun Lee, Seung Hyun Ra, Sang Moon Lee, Jung Woo Lee, Jeong Bok Kwak, Jae Choon Cho, Chi Seong Kim