Patents by Inventor Jae Chul Om
Jae Chul Om has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8268685Abstract: A NAND flash memory device and method of manufacturing the same is disclosed. Source and drain select transistor gates are recessed lower than an active region of a semiconductor substrate. A valid channel length of the source and drain select transistor gates is longer than a channel length of memory cell gates. Accordingly, an electric field between a source region and a drain region of the select transistor can be reduced. It is thus possible to prevent program disturbance from occurring in edge memory cells adjacent to the source and drain select transistors in non-selected cell strings.Type: GrantFiled: March 22, 2011Date of Patent: September 18, 2012Assignee: Hynix Semiconductor Inc.Inventors: Jae Chul Om, Nam Kyeong Kim, Se Jun Kim
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Patent number: 8106448Abstract: A method of manufacturing a NAND flash memory device. A semiconductor substrate of a portion in which a source select line SSL and a drain select line DSL will be formed is recessed selectively or entirely to a predetermined depth. Accordingly, the channel length of a gate can be increased and disturbance can be reduced. It is therefore possible to improve the reliability and yield of devices.Type: GrantFiled: April 19, 2010Date of Patent: January 31, 2012Assignee: Hynix Semiconductor Inc.Inventors: Jae Chul Om, Nam Kyeong Kim
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Patent number: 8044454Abstract: A non-volatile memory device having a SONOS structure and a manufacturing method thereof, where a conductive layer is formed between a charge trap layer and a blocking insulation layer of the SONOS structure. Therefore, when a voltage is applied to a gate, the conductive layer undergoes voltage distributions. Accordingly, a desired voltage can be applied to the blocking insulation layer, the charge trap layer and the tunnel insulating layer by controlling the effective oxide thickness (EOT) of the blocking insulation layer and the EOT of the charge trap layer and the tunnel insulating layer. It is therefore possible to improve the erase speed of a cell.Type: GrantFiled: June 23, 2009Date of Patent: October 25, 2011Assignee: Hynix Semiconductor Inc.Inventor: Jae Chul Om
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Publication number: 20110171797Abstract: A NAND flash memory device and method of manufacturing the same is disclosed. Source and drain select transistor gates are recessed lower than an active region of a semiconductor substrate. A valid channel length of the source and drain select transistor gates is longer than a channel length of memory cell gates. Accordingly, an electric field between a source region and a drain region of the select transistor can be reduced. It is thus possible to prevent program disturbance from occurring in edge memory cells adjacent to the source and drain select transistors in non-selected cell strings.Type: ApplicationFiled: March 22, 2011Publication date: July 14, 2011Applicant: Hynix Semiconductor Inc.Inventors: Jae Chul OM, Nam Kyeong Kim, Se Jun Kim
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Patent number: 7910430Abstract: A NAND flash memory device and method of manufacturing the same is disclosed. Source and drain select transistor gates are recessed lower than an active region of a semiconductor substrate. A valid channel length of the source and drain select transistor gates is longer than a channel length of memory cell gates. Accordingly, an electric field between a source region and a drain region of the select transistor can be reduced. It is thus possible to prevent program disturbance from occurring in edge memory cells adjacent to the source and drain select transistors in non-selected cell strings.Type: GrantFiled: March 4, 2008Date of Patent: March 22, 2011Assignee: Hynix Semiconductor Inc.Inventors: Jae Chul Om, Nam Kyeong Kim, Se Jun Kim
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Patent number: 7851311Abstract: Non-volatile memory devices and a method of manufacturing the same, wherein data storage of two bits per cell is enabled and the devices can pass the limit in terms of layout, whereby channel length can be controlled. The non-volatile memory device includes gate lines formed in one direction on a semiconductor substrate in which trenches are formed, wherein the gate lines gap-fill the trenches, a dielectric layer formed between the semiconductor substrate and the gate lines, bit separation insulating layers formed between the semiconductor substrate and the dielectric layer under the trenches, and isolation structures formed by etching the trenches, and the dielectric layer and the semiconductor substrate between the trenches in a line form vertical to the gate lines and gap-filling an insulating layer.Type: GrantFiled: July 2, 2009Date of Patent: December 14, 2010Assignee: Hynix Semiconductor Inc.Inventors: Nam-Kyeong Kim, Jae Chul Om
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Publication number: 20100200902Abstract: A method of manufacturing a NAND flash memory device. A semiconductor substrate of a portion in which a source select line SSL and a drain select line DSL will be formed is recessed selectively or entirely to a predetermined depth. Accordingly, the channel length of a gate can be increased and disturbance can be reduced. It is therefore possible to improve the reliability and yield of devices.Type: ApplicationFiled: April 19, 2010Publication date: August 12, 2010Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Jae Chul Om, Nam Kyeong Kim
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Patent number: 7727839Abstract: A method of manufacturing a NAND flash memory device is disclosed. A semiconductor substrate of a portion in which a source select line SSL and a drain select line DSL will be formed is recessed selectively or entirely to a predetermined depth. Accordingly, the channel length of a gate can be increased and disturbance can be reduced. It is therefore possible to improve the reliability and yield of devices.Type: GrantFiled: December 28, 2006Date of Patent: June 1, 2010Assignee: Hynix Semiconductor Inc.Inventors: Jae Chul Om, Nam Kyeong Kim
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Publication number: 20090269895Abstract: Non-volatile memory devices and a method of manufacturing the same, wherein data storage of two bits per cell is enabled and the devices can pass the limit in terms of layout, whereby channel length can be controlled. The non-volatile memory device includes gate lines formed in one direction on a semiconductor substrate in which trenches are formed, wherein the gate lines gap-fill the trenches, a dielectric layer formed between the semiconductor substrate and the gate lines, bit separation insulating layers formed between the semiconductor substrate and the dielectric layer under the trenches, and isolation structures formed by etching the trenches, and the dielectric layer and the semiconductor substrate between the trenches in a line form vertical to the gate lines and gap-filling an insulating layer.Type: ApplicationFiled: July 2, 2009Publication date: October 29, 2009Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Nam Kyeong Kim, Jae Chul Om
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Publication number: 20090261404Abstract: A non-volatile memory device having a SONOS structure and a manufacturing method thereof, where a conductive layer is formed between a charge trap layer and a blocking insulation layer of the SONOS structure. Therefore, when a voltage is applied to a gate, the conductive layer undergoes voltage distributions. Accordingly, a desired voltage can be applied to the blocking insulation layer, the charge trap layer and the tunnel insulating layer by controlling the effective oxide thickness (EOT) of the blocking insulation layer and the EOT of the charge trap layer and the tunnel insulating layer. It is therefore possible to improve the erase speed of a cell.Type: ApplicationFiled: June 23, 2009Publication date: October 22, 2009Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Jae Chul Om
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Patent number: 7595239Abstract: A method of fabricating a non-volatile memory device forming a first polysilicon film over a semiconductor substrate; forming a mitigation film over the first polysilicon film; forming a mask film over the mitigation film; etching the mask film, the mitigation film, and the first polysilicon film to form a first trench that defines first and second floating gates; forming an interlayer film over the mask film, the interlayer film filling the first trench to form a vertical structure; anisotropically etching the vertical structure of the interlayer film to form second and third trenches, the second trench being provided between the first floating gate and the etched vertical structure, the third trench being provided between the second floating gate the and etched vertical structure; forming a dielectric film over the first and second floating gate and the vertical structure, the dielectric film coating sidewalls of the second and third trenches; and forming a control gate layer over the dielectric film, the cType: GrantFiled: April 26, 2006Date of Patent: September 29, 2009Assignee: Hynix Semiconductor Inc.Inventor: Jae Chul Om
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Patent number: 7573089Abstract: Non-volatile memory devices and a method of manufacturing the same, wherein data storage of two bits per cell is enabled and the devices can pass the limit in terms of layout, whereby channel length can be controlled. The non-volatile memory device includes gate lines formed in one direction on a semiconductor substrate in which trenches are formed, wherein the gate lines gap-fill the trenches, a dielectric layer formed between the semiconductor substrate and the gate lines, bit separation insulating layers formed between the semiconductor substrate and the dielectric layer under the trenches, and isolation structures formed by etching the trenches, and the dielectric layer and the semiconductor substrate between the trenches in a line form vertical to the gate lines and gap-filling an insulating layer.Type: GrantFiled: December 6, 2006Date of Patent: August 11, 2009Assignee: Hynix Semiconductor Inc.Inventors: Nam Kyeong Kim, Jae Chul Om
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Patent number: 7566618Abstract: A non-volatile memory device having a SONOS structure and a manufacturing method thereof, where a conductive layer is formed between a charge trap layer and a blocking insulation layer of the SONOS structure. Therefore, when a voltage is applied to a gate, the conductive layer undergoes voltage distributions. Accordingly, a desired voltage can be applied to the blocking insulation layer, the charge trap layer and the tunnel insulating layer by controlling the effective oxide thickness (EOT) of the blocking insulation layer and the EOT of the charge trap layer and the tunnel insulating layer. It is therefore possible to improve the erase speed of a cell.Type: GrantFiled: March 8, 2007Date of Patent: July 28, 2009Assignee: Hynix Semiconductor Inc.Inventor: Jae Chul Om
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Patent number: 7456466Abstract: A NAND flash memory device and method of manufacturing the same is disclosed. Source and drain select transistor gates are recessed lower than an active region of a semiconductor substrate. A valid channel length of the source and drain select transistor gates is longer than a channel length of memory cell gates. Accordingly, an electric field between a source region and a drain region of the select transistor can be reduced. It is thus possible to prevent program disturbance from occurring in edge memory cells adjacent to the source and drain select transistors in non-selected cell strings.Type: GrantFiled: June 2, 2006Date of Patent: November 25, 2008Assignee: Hynix Semiconductor Inc.Inventors: Jae Chul Om, Nam Kyeong Kim, Se Jun Kim
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Publication number: 20080153227Abstract: A NAND flash memory device and method of manufacturing the same is disclosed. Source and drain select transistor gates are recessed lower than an active region of a semiconductor substrate. A valid channel length of the source and drain select transistor gates is longer than a channel length of memory cell gates. Accordingly, an electric field between a source region and a drain region of the select transistor can be reduced. It is thus possible to prevent program disturbance from occurring in edge memory cells adjacent to the source and drain select transistors in non-selected cell strings.Type: ApplicationFiled: March 4, 2008Publication date: June 26, 2008Applicant: Hynix Semiconductor Inc.Inventors: Jae Chul Om, Nam Kyeong Kim, Se Jun Kim
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Publication number: 20080093661Abstract: A non-volatile memory device comprises a substrate, a tunneling layer over the substrate, a charge trapping layer comprising a stoichiometric silicon nitride layer and a silicon-rich silicon nitride layer over the tunneling layer, a blocking layer over the charge trapping layer, and a control gate electrode over the blocking layer.Type: ApplicationFiled: June 28, 2007Publication date: April 24, 2008Applicant: Hynix Semiconductor Inc.Inventors: Moon Sig Joo, Hong Seon Yang, Jae Chul Om, Seung Ho Pyi, Seung Ryong Lee, Yong Top Kim
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Publication number: 20080006873Abstract: A non-volatile memory device having a SONOS structure and a manufacturing method thereof, where a conductive layer is formed between a charge trap layer and a blocking insulation layer of the SONOS structure. Therefore, when a voltage is applied to a gate, the conductive layer undergoes voltage distributions. Accordingly, a desired voltage can be applied to the blocking insulation layer, the charge trap layer and the tunnel insulating layer by controlling the effective oxide thickness (EOT) of the blocking insulation layer and the EOT of the charge trap layer and the tunnel insulating layer. It is therefore possible to improve the erase speed of a cell.Type: ApplicationFiled: March 8, 2007Publication date: January 10, 2008Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Jae Chul Om
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Publication number: 20070264775Abstract: Non-volatile memory devices and a method of manufacturing the same, wherein data storage of two bits per cell is enabled and the devices can pass the limit in terms of layout, whereby channel length can be controlled. The non-volatile memory device includes gate lines formed in one direction on a semiconductor substrate in which trenches are formed, wherein the gate lines gap-fill the trenches, a dielectric layer formed between the semiconductor substrate and the gate lines, bit separation insulating layers formed between the semiconductor substrate and the dielectric layer under the trenches, and isolation structures formed by etching the trenches, and the dielectric layer and the semiconductor substrate between the trenches in a line form vertical to the gate lines and gap-filling an insulating layer.Type: ApplicationFiled: December 6, 2006Publication date: November 15, 2007Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Nam Kyeong Kim, Jae Chul Om
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Publication number: 20070254433Abstract: A method of fabricating a non-volatile memory device forming a first polysilicon film over a semiconductor substrate; forming a mitigation film over the first polysilicon film; forming a mask film over the mitigation film; etching the mask film, the mitigation film, and the first polysilicon film to form a first trench that defines first and second floating gates; forming an interlayer film over the mask film, the interlayer film filling the first trench to form a vertical structure; anisotropically etching the vertical structure of the interlayer film to form second and third trenches, the second trench being provided between the first floating gate and the etched vertical structure, the third trench being provided between the second floating gate the and etched vertical structure; forming a dielectric film over the first and second floating gate and the vertical structure, the dielectric film coating sidewalls of the second and third trenches; and forming a control gate layer over the dielectric film, the cType: ApplicationFiled: April 26, 2006Publication date: November 1, 2007Applicant: Hynix semiconductor, Inc.Inventor: Jae Chul Om
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Publication number: 20070155098Abstract: A method of manufacturing a NAND flash memory device is disclosed. A semiconductor substrate of a portion in which a source select line SSL and a drain select line DSL will be formed is recessed selectively or entirely to a predetermined depth. Accordingly, the channel length of a gate can be increased and disturbance can be reduced. It is therefore possible to improve the reliability and yield of devices.Type: ApplicationFiled: December 28, 2006Publication date: July 5, 2007Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Jae Chul Om, Nam Kyeong Kim