Patents by Inventor Jae-chul Ryu

Jae-chul Ryu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060105153
    Abstract: Provided is a method of manufacturing a printed circuit board. In an embodiment, the method includes forming a prepreg layer via a reel method, forming a conductive film for forming a circuit pattern on at least one surface of the prepreg layer; and forming a predetermined circuit pattern on the conductive film. In an embodiment, the prepreg layer has a thickness of at most about 0.15 mm and contains a fiber material and a resin material. In an embodiment, the content of the resin material in the prepreg layer is about 70% or less by volume. In an embodiment, the prepreg layer is composed of at least one prepreg layer.
    Type: Application
    Filed: October 5, 2005
    Publication date: May 18, 2006
    Applicant: Samsung Techwin Co., Ltd.
    Inventors: Chang-soo Jang, Jae-chul Ryu, Hyoung-ho Roh, Dong-kwan Won
  • Publication number: 20060038280
    Abstract: A parent or master substrate for a semiconductor package is provided, which can provide a plurality of unit substrates by cutting into pieces for producing a semiconductor device. The parent substrate includes an insulation layer, conductor patterns formed on first and second surfaces of the insulation layer, and PSR (photo solder resist) layers respectively formed on the first and second surfaces of the insulation layers and covering the conductor patterns. The parent substrate includes an upper part and a lower part divided by a reference surface which passes through the center of the insulation layer. When an equivalent thermal expansion coefficient ?upper of the upper part is defined by the Equation of ? upper = ? i = 1 n ? ? i × E i × v i ? i = 1 n ? E i × v i , where ?i is respective thermal expansion coefficients of, Ei is respective elastic moduli of, and vi is respective volume ratios of first through nth components constituting the upper part (e.g.
    Type: Application
    Filed: May 20, 2005
    Publication date: February 23, 2006
    Inventors: Chang-soo Jang, Jae-chul Ryu, Dong-kwan Won
  • Publication number: 20060016619
    Abstract: There are provided a printed circuit board having a structure for relieving a stress concentration on an outer most lead of leads, due to a difference in thermal expansion coefficients between the semiconductor device and the printed circuit board when the semiconductor device is mounted on the printed circuit board. The printed circuit board includes an inner lead portion to be connected to the semiconductor device. The inner lead portion includes a plurality of leads, arranged in parallel with a same pitch in a predetermined area, and additional leads located near both ends of the predetermined area in which the plurality of leads are arranged in parallel, respectively, wherein each of the plurality of leads has a pitch smaller than 30 ?m and a width of the additional lead is wider than 20 ?m. There are also provided a semiconductor chip package equipped with the printed circuit board according to the present invention.
    Type: Application
    Filed: June 27, 2005
    Publication date: January 26, 2006
    Applicant: Samsung Techwin Co., Ltd.
    Inventors: Chang-soo Jang, Jae-chul Ryu, Seong-young Han
  • Patent number: 6074728
    Abstract: A multi-layered circuit substrate and a manufacturing method thereof comprising the steps of coating the upper surface of a substrate with a photosensitive insulating layer; exposing and developing the photosensitive insulating layer to form a photosensitive insulating layer of predetermined pattern and pattern spaces; forming a conductive layer by printing a conductive ink in the pattern spaces; and forming a plurality of layers by performing the previous steps, each layer comprising a photosensitive insulating layer of predetermined pattern and pattern spaces and a conductive layer formed in the pattern spaces.
    Type: Grant
    Filed: December 16, 1997
    Date of Patent: June 13, 2000
    Assignee: Samsung Aerospace Industries, Ltd.
    Inventor: Jae-chul Ryu
  • Patent number: 5877941
    Abstract: An IC card and a method of fabricating the same are provided in which the IC card substrate is formed of a blackened metal core plate to improve thermal, electrical and mechanical stability of the IC card.
    Type: Grant
    Filed: April 24, 1997
    Date of Patent: March 2, 1999
    Assignee: Samsung Aerospace Industries, Ltd.
    Inventor: Jae-chul Ryu
  • Patent number: 5747222
    Abstract: A multi-layered circuit substrate and a manufacturing method thereof comprising the steps of coating the upper surface of a substrate with a photosensitive insulating layer; exposing and developing the photosensitive insulating layer to form a photosensitive insulating layer of predetermined pattern and pattern spaces; forming a conductive layer by printing a conductive ink in the pattern spaces; and forming a plurality of layers by performing the previous steps, each layer comprising a photosensitive insulating layer of predetermined pattern and pattern spaces and a conductive layer formed in the pattern spaces.
    Type: Grant
    Filed: September 11, 1996
    Date of Patent: May 5, 1998
    Assignee: Samsung Aerospace Industries, Ltd.
    Inventor: Jae-chul Ryu