Patents by Inventor Jae-dong Lee

Jae-dong Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100062548
    Abstract: A photo key has a plurality of first regions spaced apart from one another on a semiconductor substrate, and a second region surrounding the first regions, and one of the first regions and the second region constitutes a plurality of photo key regions spaced apart from one another. Each of the photo key regions includes a plurality of first conductive patterns spaced apart from one another; and a plurality of second conductive patterns interposed between the first conductive patterns.
    Type: Application
    Filed: June 1, 2009
    Publication date: March 11, 2010
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byoung-ho Kwon, Chang-ki Hong, Bo-un Yoon, Jae-dong Lee, Sang-jin Kim
  • Patent number: 7634487
    Abstract: The present invention is to provide a system and a method for index reorganization using a partial index transfer in a spatial data warehouse that minimize costs of search, split and readjustment for the index reorganization by organizing and transferring clusters with partial indexes in conformity with an index structure so that the partial indexes can be inserted directly into the existing index, thus ensuring continuous and stable data processes, the index reorganization method comprising: a first step of clustering data extracted from the source database in conformity with an index structure via the builder; a second step of generating partial indexes and transferring the partial indexes to a cluster generated according to the clustering; a third step of recording the transferred partial indexes in physically consecutive spaces, not allocated, in the spatial data warehouse server; and a fourth step of inserting the recorded partial indexes in an existing index.
    Type: Grant
    Filed: May 12, 2006
    Date of Patent: December 15, 2009
    Assignee: Inha-Industry Partnership Institute
    Inventors: Hae Young Bae, Jae Dong Lee, Young Hwan Oh, Kyoung Bae Kim, Myoung Keun Kim, Soon Young Park, Ho Seok Kim, Yong Il Jang, Byeong Seob You, Sang Hoon Eo, Young Cheol Jeong
  • Publication number: 20090280641
    Abstract: An insulation layer may be formed on an object having a contact region. The insulation layer may be partially etched to form an opening exposing the contact region. A material layer including silicon and oxygen may be formed on the exposed contact region. A metal layer may be formed on the material layer including silicon and oxygen. The material layer including silicon and oxygen may be reacted with the metal layer to form a metal oxide silicide layer at least on the contact region. A conductive layer may be formed on the metal oxide silicide layer to fill up the opening.
    Type: Application
    Filed: May 7, 2009
    Publication date: November 12, 2009
    Inventors: Dae-Hyuk Kang, Young-Hoo Kim, Chang-Ki Hong, Kun-Tack Lee, Jae-Dong Lee, Dae-Hong Eom, Jeong-Nam Han
  • Publication number: 20090155991
    Abstract: A method of fabricating a contact plug of a semiconductor device is provided, the method includes forming a gate pattern on a substrate, forming a capping pattern to cover an upper surface and sidewalls of the gate pattern, forming an interlayer insulation layer on the substrate such that the interlayer insulation layer exposes an upper surface of the capping pattern, and removing a portion of the capping pattern and the interlayer insulation layer such that the upper surface of the capping pattern is planarized.
    Type: Application
    Filed: November 13, 2008
    Publication date: June 18, 2009
    Inventors: Jong-Won Lee, Sang-Yeob Han, Chang-Ki Hong, Bo-Un Yoon, Jae-Dong Lee
  • Publication number: 20090068839
    Abstract: A slurry, chemical mechanical polishing (CMP) method using the slurry, and method of forming metal wiring using the slurry. The slurry may include a polishing agent, an oxidant, and at least one defect inhibitor to protect the metal film. The CMP method and method of forming metal wiring may employ one or two slurries with at least one of the slurries including at least one defect inhibitor.
    Type: Application
    Filed: June 19, 2008
    Publication date: March 12, 2009
    Inventors: Sung-Jun Kim, Jeong-Heon Park, Chang-Ki Hong, Jae-Dong Lee
  • Patent number: 7498263
    Abstract: A method for forming a planarized inter-metal insulation film is provided. The method includes applying a CMP process to an insulation film as controlled by a polish-stop layer pattern formed on an underlying metal wiring pattern. A PAE based material may be used to form the polish-stop layer.
    Type: Grant
    Filed: December 12, 2005
    Date of Patent: March 3, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Se-rah Yun, Chang-ki Hong, Jae-dong Lee
  • Publication number: 20090011599
    Abstract: Slurry compositions for selectively polishing silicon nitride relative to silicon oxide, methods of polishing a silicon nitride layer and methods of manufacturing a semiconductor device using the same are provided. The slurry compositions include a first agent for reducing an oxide polishing rate, an abrasive particle and water, and the first agent includes poly(acrylic acid). The slurry composition may have a high polishing selectivity of silicon nitride relative to silicon oxide to be employed in selectively polishing a silicon nitride layer in a semiconductor manufacturing process.
    Type: Application
    Filed: July 3, 2008
    Publication date: January 8, 2009
    Inventors: Jong-Won Lee, Sang-Yeob Han, Chang-Ki Hong, Jae-Dong Lee
  • Publication number: 20090001051
    Abstract: A slurry composition for polishing metal includes a polymeric polishing accelerating agent, the polymeric polishing accelerating agent including a backbone of hydrocarbon and a side substituent having at least one of a sulfonate ion (SO3?) and a sulfate ion (OSO3?), and an acidic aqueous solution.
    Type: Application
    Filed: June 26, 2008
    Publication date: January 1, 2009
    Inventors: Jong-Won Lee, Sang-Yeob Han, Chang-Ki Hong, Bo-Un Yoon, Jae-Dong Lee
  • Publication number: 20080277767
    Abstract: A method of planarizing the surface of a semiconductor substrate to reduce the occurrence of a dishing phenomenon. A patterned etch stop layer defining a trench region is formed on a substrate. The substrate is etched to form a trench region, and a medium material layer and an oxide layer are subsequently formed on the substrate, filling the trench region. Chemical mechanical polishing (CMP) is performed on the oxide layer until the medium material layer is exposed. CMP is then performed until the patterned etch stop layer is exposed and a planarized oxide layer is formed. Because the medium material layer has a higher removal rate during CMP than the oxide layer, occurrences of the dishing phenomenon are reduced. A slurry including an anionic surfactant is used to increase the CMP removal ratio of the medium material layer to the oxide layer.
    Type: Application
    Filed: July 17, 2008
    Publication date: November 13, 2008
    Inventors: Jae-Dong Lee, Yong-Pil Han, Chang-Ki Hong
  • Patent number: 7442646
    Abstract: A slurry, chemical mechanical polishing (CMP) method using the slurry, and method of forming metal wiring using the slurry. The slurry may include a polishing agent, an oxidant, and at least one defect inhibitor to protect the metal film. The CMP method and method of forming metal wiring may employ one or two slurries with at least one of the slurries including at least one defect inhibitor.
    Type: Grant
    Filed: March 11, 2005
    Date of Patent: October 28, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Jun Kim, Jeong-Heon Park, Chang-Ki Hong, Jae-Dong Lee
  • Patent number: 7440977
    Abstract: The present invention provides a recovery method using extendible hashing-based cluster logs in a shared-nothing spatial database cluster, which eliminates the duplication of cluster logs required for cluster recovery in a shared-nothing database cluster, so that recovery time is decreased, thus allowing the shared-nothing spatial database cluster system to continuously provide stable service. In the recovery method, if a failure occurs in a predetermined node, a second node in a group, including the node, records cluster logs in main memory on the basis of extendible hashing. If the node that has failed recovers itself using a local log, the second node in the group transmits cluster logs in packets to a recovery node that is the failed node. If the recovery node reflects the received cluster logs and maintains consistency with other nodes in the group, the recovery node resumes normal service.
    Type: Grant
    Filed: June 20, 2005
    Date of Patent: October 21, 2008
    Assignee: Inha-Industry Partnership Institute
    Inventors: Hae-Young Bae, Jae-Dong Lee, Young-Hwan Oh, Gyoung-Bae Kim, Myoung-Keun Kim, Soon-Young Park, Ho-Seok Kim, Yong-Il Jang
  • Publication number: 20080233216
    Abstract: The extract of Siegesbeckiae herba of the present invention showed potent inhibitory effect on the dissociation of proteoglycan and type II collagen in chondrocyte and cartilage tissue and protecting effect on cartilage due to the inhibition of MMP-1, MMP-3 and MMP-13 activity and the restoring effect on cartilage tissue, the anti-inflammatory and antiphlogistic effect in edema animal model, anti-inflammatory effect confirmed by the inhibition test on PGE2 activity through COX-2 inhibition and the inhibition test of the reproduction of TNF-? and NO, it can be used as the therapeutics or health food for treating and preventing arthritic disease.
    Type: Application
    Filed: February 24, 2006
    Publication date: September 25, 2008
    Applicant: Industry Academic Cooperation Foundation Of Kyunghee University
    Inventors: Dong-Suk Park, Myung Chul Yoo, Do-Young Choi, Jae-Dong Lee, Yong-Baik Cho, Nam-Jae Kim, Eun-Mi Cho, Jeong-Eun Huh, Yong-Hyeon Baek, Seung Jae Hong
  • Patent number: 7413959
    Abstract: A method of planarizing the surface of a semiconductor substrate to reduce the occurrence of a dishing phenomenon. A patterned etch stop layer defining a trench region is formed on a substrate. The substrate is etched to form a trench region, and a medium material layer and an oxide layer are subsequently formed on the substrate, filling the trench region. Chemical mechanical polishing (CMP) is performed on the oxide layer until the medium material layer is exposed. CMP is then performed until the patterned etch stop layer is exposed and a planarized oxide layer is formed. Because the medium material layer has a higher removal rate during CMP than the oxide layer, occurrences of the dishing phenomenon are reduced. A slurry including an anionic surfactant is used to increase the CMP removal ratio of the medium material layer to the oxide layer.
    Type: Grant
    Filed: April 21, 2003
    Date of Patent: August 19, 2008
    Assignee: Samsung Electronics Co., L.T.D.
    Inventors: Jae-Dong Lee, Yong-Pil Han, Chang-Ki Hong
  • Patent number: 7338352
    Abstract: A slurry delivery system, a chemical mechanical polishing (CMP) apparatus, and method for using the same are provided. An apparatus for supplying slurry to a polishing unit may include a first feed line through which an abrasive may be supplied at a first velocity. A velocity-changing member may be connected to the first feed line, and/or a velocity of the abrasive may be changed from the first velocity to. the second velocity different from the first velocity by the velocity-changing member. A second feed line may be connected to the velocity-changing member and/or an additive may be supplied through the second feed line. A supply line may be connected to the velocity-changing member. A slurry, which may be a mixture of the abrasive and/or the additive, may be supplied to a polishing unit through the supply line. Accordingly, the slurry may be more uniformly mixed and/or supplied to a polishing unit.
    Type: Grant
    Filed: May 16, 2006
    Date of Patent: March 4, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Choong-Kee Seong, Chang-Ki Hong, Jae-Dong Lee
  • Patent number: 7294516
    Abstract: A test pattern and a method of controlling a CMP using the same are provided. The test pattern is disposed on a monitoring region of a semiconductor substrate having a main region and a monitoring region. The test pattern includes a planar region and a pattern region. The method comprises setting a correlation between a step difference of a test pattern and an etched thickness of a main pattern, then applying the CMP to a semiconductor substrate having the test pattern and the main pattern for a predetermined time. The step difference of the test pattern is measured and the etched thickness of the main pattern, which corresponds to the step difference of the test pattern, is determined from the correlation. A polishing time is corrected by comparing the determined etched thickness of the main pattern with a reference value, and the corrected polishing time is applied to a subsequent lot or subsequent substrate.
    Type: Grant
    Filed: February 10, 2005
    Date of Patent: November 13, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeong-Heon Park, Bo-Un Yoon, Jae-Dong Lee
  • Patent number: 7247256
    Abstract: A first chemical mechanical polishing (CMP) slurry includes a polishing agent, an oxidant, a pH control additive, and an oxide film removal retarder which reduces a removal rate of the silicon oxide film. A second chemical mechanical polishing (CMP) slurry includes a polishing agent, an oxidant, a pH control additive, an oxide film removal retarder which reduces a removal rate of silicon oxide, and a defect prevention agent which inhibits scratch defects and/or corrosion defects at a surface of an aluminum film. In a one-step CMP process, either of the first or second slurry is used throughout CMP of an aluminum layer until an upper surface of an underlying silicon oxide layer is exposed. In a two-step CMP process, the first slurry is used in an initial CMP of the aluminum layer, and then the second slurry is used in a subsequent CMP until the upper surface of the underlying silicon layer is exposed.
    Type: Grant
    Filed: October 12, 2004
    Date of Patent: July 24, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeong-heon Park, Jae-dong Lee, Sung-jun Kim, Chang-ki Hong
  • Patent number: 7244649
    Abstract: A method for manufacturing a capacitor is disclosed. An etch-stop layer or a polishing stop layer is employed to protect a storage electrode of the capacitor from being damaged by a chemical mechanical polishing process or an etch-back process during its fabrication.
    Type: Grant
    Filed: December 9, 2004
    Date of Patent: July 17, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Dong Lee, Chang-Ki Hong, Young-Rae Park
  • Publication number: 20070145012
    Abstract: Disclosed is a slurry and method for chemical-mechanical polishing operation. The slurry may contain abrasive particles, an oxidizer, a pH controller, a chelating agent and water. The viscosity of the slurry may be in the range of about 1.0 cP—about 1.05 cP, so that the step difference may be reduced between regions with patterns and without patterns even after completing the chemical-mechanical polishing operation. A permissible rate of depth of focus (DOF) may not need to be controlled in the subsequent photolithography operation, which may enable the subsequent photolithography operation to be conducted by an optical system with relatively low DOF.
    Type: Application
    Filed: October 4, 2006
    Publication date: June 28, 2007
    Inventors: Joon-Sang Park, Jong-Won Lee, Chang-Ki Hong, Bo-Un Yoon, Jae-Dong Lee
  • Patent number: 7144815
    Abstract: A polishing slurry including an abrasive, deionized water, a pH controlling agent, and polyethylene imine, can control the removal rates of a silicon oxide layer and a silicon nitride layer which are simultaneously exposed during chemical mechanical polishing (CMP) of a conductive layer. A relative ratio of the removal rate of the silicon oxide layer to that of the silicon nitride layer can be controlled by controlling an amount of the choline derivative.
    Type: Grant
    Filed: January 15, 2004
    Date of Patent: December 5, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-dong Lee, Bo-un Yoon, Sang-rok Hah
  • Patent number: 7144301
    Abstract: For planarizing an IC (integrate circuit) material, a first slurry is dispensed for a first planarization of the IC material using the first slurry, and a second slurry is dispensed for a second planarization of the IC material using the second slurry. The first and second slurries are different. For example, the first slurry is silica based for faster planarization during the first planarization. Thereafter, the second planarization is performed with the second slurry that is ceria based with higher planarity for attaining sufficient planarization of the IC material.
    Type: Grant
    Filed: September 22, 2004
    Date of Patent: December 5, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwang-Bok Kim, Jae-Kwang Choi, Yong-Sun Ko, Chang-Ki Hong, Kyung-Hyun Kim, Jae-Dong Lee