Abstract: A method of forming patterns of a semiconductor device includes forming a hard mask layer and a first sacrificial layer over a first region and a second region of a semiconductor substrate, etching the first sacrificial layer to form a first sacrificial pattern having a first width in the first region and second sacrificial patterns having a second width in the second region, wherein the second width is narrower than the first width, forming a first spacer surrounding sidewalls of the first sacrificial pattern and a second spacer surrounding sidewalls of the second sacrificial patterns, removing the first and the second sacrificial patterns; and etching the first and second spacers.

Abstract: A method of forming patterns of a semiconductor device includes forming a hard mask layer and a first sacrificial layer over a first region and a second region of a semiconductor substrate, etching the first sacrificial layer to form a first sacrificial pattern having a first width in the first region and second sacrificial patterns having a second width in the second region, wherein the second width is narrower than the first width, forming a first spacer surrounding sidewalls of the first sacrificial pattern and a second spacer surrounding sidewalls of the second sacrificial patterns, removing the first and the second sacrificial patterns; and etching the first and second spacers.

Abstract: Disclosed is a photoresist coating apparatus capable of preventing a substrate from being contaminated and preventing a pattern bridge phenomenon from being created in the substrate during an exposure process by shielding backflow of photoresist through forcibly exhausting photoresist to an exterior. The photoresist coating apparatus includes a vacuum chuck for holding a substrate by using vacuum, a driving motor connected to the vacuum chuck through an arm, a first nozzle for coating photoresist onto the substrate, a second nozzle for performing a rinse process, a bath surrounding the vacuum chuck to prevent photoresist from being discharged to an exterior, a first drain pipe connected to both lower ends of the bath in order to discharge photoresist contained in the bath, and a photoresist discharge section for forcibly discharging photoresist contained in the bath to the exterior.

Abstract: Disclosed is a photoresist coating apparatus capable of preventing a substrate from being contaminated and preventing a pattern bridge phenomenon from being created in the substrate during an exposure process by shielding backflow of photoresist through forcibly exhausting photoresist to an exterior. The photoresist coating apparatus includes a vacuum chuck for holding a substrate by using vacuum, a driving motor connected to the vacuum chuck through an arm, a first nozzle for coating photoresist onto the substrate, a second nozzle for performing a rinse process, a bath surrounding the vacuum chuck to prevent photoresist from being discharged to an exterior, a first drain pipe connected to both lower ends of the bath in order to discharge photoresist contained in the bath, and a photoresist discharge section for forcibly discharging photoresist contained in the bath to the exterior.

Abstract: A flash memory device having improved gate capacitive coupling ratio between a floating gate and a control gate and a fabrication method therefor. The disclosed flash memory device comprises a semiconductor substrate having a first trench with a width including an active region and an isolation region at either side thereof; an isolation layer formed on the isolation regions of the first trench; a second trench in the first trench defined by the isolation layer and exposing only the active region; a groove-shaped floating gate formed on the surface of the second trench and having a tunnel oxide layer on the lower part thereof; a control gate formed on the floating gate and having a gate insulating layer on the lower part thereof; a source region and a drain region formed in the substrate at both sides of the floating gate; and metal wirings formed to be in contact with the source and drain regions, respectively, through the isolation layer on the substrate.

Abstract: A flash memory device having improved gate capacitive coupling ratio between a floating gate and a control gate and a fabrication method therefor. The disclosed flash memory device comprises a semiconductor substrate having a first trench with a width including an active region and an isolation region at either side thereof; an isolation layer formed on the isolation regions of the first trench; a second trench in the first trench defined by the isolation layer and exposing only the active region; a groove-shaped floating gate formed on the surface of the second trench and having a tunnel oxide layer on the lower part thereof; a control gate formed on the floating gate and having a gate insulating layer on the lower part thereof; a source region and a drain region formed in the substrate at both sides of the floating gate; and metal wirings formed to be in contact with the source and drain regions, respectively, through the isolation layer on the substrate.

Abstract: A flash memory device having improved gate capacitive coupling ratio between a floating gate and a control gate and a fabrication method therefor. The disclosed flash memory device comprises a semiconductor substrate having a first trench with a width including an active region and an isolation region at either side thereof; an isolation layer formed on the isolation regions of the first trench; a second trench in the first trench defined by the isolation layer and exposing only the active region; a groove-shaped floating gate formed on the surface of the second trench and having a tunnel oxide layer on the lower part thereof; a control gate formed on the floating gate and having a gate insulating layer on the lower part thereof; a source region and a drain region formed in the substrate at both sides of the floating gate; and metal wirings formed to be in contact with the source and drain regions, respectively, through the isolation layer on the substrate.

Abstract: A flash memory device having improved gate capacitive coupling ratio between a floating gate and a control gate and a fabrication method therefor. The disclosed flash memory device comprises a semiconductor substrate having a first trench with a width including an active region and an isolation region at either side thereof; an isolation layer formed on the isolation regions of the first trench; a second trench in the first trench defined by the isolation layer and exposing only the active region; a groove-shaped floating gate formed on the surface of the second trench and having a tunnel oxide layer on the lower part thereof; a control gate formed on the floating gate and having a gate insulating layer on the lower part thereof; a source region and a drain region formed in the substrate at both sides of the floating gate; and metal wirings formed to be in contact with the source and drain regions, respectively, through the isolation layer on the substrate.