Abstract: Each of memory blocks of a nonvolatile memory device includes a memory cell region including first metal pads, first memory cells of a first portion of pillar, and second memory cells of a second portion of the pillar, and a peripheral circuit region including second metal pads, a row decoder, and a page buffer. When performing program operations based on consecutive addresses at a memory block selected from the memory blocks, the nonvolatile memory device sequentially completes first program operations of non-adjacent memory cells not adjacent to a boundary of the first portion and the second portion from among the first and second memory cells and then completes a second program operation of an adjacent memory cell adjacent to the boundary. The peripheral circuit region is vertically connected to the memory cell region by the first metal pads and the second metal pads directly.

Abstract: An operation method of a nonvolatile memory device includes receiving a read command and an address, increasing a voltage applied to an unselected word line from an off voltage to a read pass voltage during a setup phase in response to the read command, increasing a voltage applied to an unselected string selection line from the off voltage to a pre-pulse voltage during a first setup phase of the setup phase, increasing a voltage applied to an unselected ground selection line from the off voltage to the pre-pulse voltage during the first setup phase, applying a read voltage to a selected word line to read data corresponding to the address, during a sensing phase following the setup phase, and outputting the read data through data lines after the sensing phase. During the setup phase, a slope of the voltage applied to the unselected word line is varied.

Abstract: An operation method of a nonvolatile memory device includes receiving a read command and an address, increasing a voltage applied to an unselected word line from an off voltage to a read pass voltage during a setup phase in response to the read command, increasing a voltage applied to an unselected string selection line from the off voltage to a pre-pulse voltage during a first setup phase of the setup phase, increasing a voltage applied to an unselected ground selection line from the off voltage to the pre-pulse voltage during the first setup phase, applying a read voltage to a selected word line to read data corresponding to the address, during a sensing phase following the setup phase, and outputting the read data through data lines after the sensing phase. During the setup phase, a slope of the voltage applied to the unselected word line is varied.

Abstract: Each of memory blocks of a nonvolatile memory device includes a memory cell region including first metal pads, first memory cells of a first portion of pillar, and second memory cells of a second portion of the pillar, and a peripheral circuit region including second metal pads, a row decoder, and a page buffer. When performing program operations based on consecutive addresses at a memory block selected from the memory blocks, the nonvolatile memory device sequentially completes first program operations of non-adjacent memory cells not adjacent to a boundary of the first portion and the second portion from among the first and second memory cells and then completes a second program operation of an adjacent memory cell adjacent to the boundary. The peripheral circuit region is vertically connected to the memory cell region by the first metal pads and the second metal pads directly.

Abstract: Each of memory blocks of a nonvolatile memory device includes a memory cell region including first metal pads, first memory cells of a first portion of pillar, and second memory cells of a second portion of the pillar, and a peripheral circuit region including second metal pads, a row decoder, and a page buffer. When performing program operations based on consecutive addresses at a memory block selected from the memory blocks, the nonvolatile memory device sequentially completes first program operations of non-adjacent memory cells not adjacent to a boundary of the first portion and the second portion from among the first and second memory cells and then completes a second program operation of an adjacent memory cell adjacent to the boundary. The peripheral circuit region is vertically connected to the memory cell region by the first metal pads and the second metal pads directly.

Abstract: A solid state drive and a method for accessing the metadata are provided. The solid state drive includes different kinds of first and second memories and a memory controller which controls the first and second memories, wherein the memory controller receives a metadata access request from a host, and includes a condition checker which determines conditions of the first and second memories in response to the metadata access request and selects at least one of the conditions, and the memory controller accesses to the memory selected by the condition checker.

Abstract: A storage device includes a first nonvolatile memory chip; a second nonvolatile memory chip; and a controller. The controller may include a processor configured to execute a flash translation layer (FTL) loaded onto an on-chip memory; an ECC engine configured to generate first parity bits for data and to selectively generate second parity bits for the data, under control of the processor; and a nonvolatile memory interface circuit configured to transmit the data and the first parity bits to the first nonvolatile memory chip, and to selectively transmit the second parity bits selectively generated to the second nonvolatile memory chip.

Abstract: Each of memory blocks of a nonvolatile memory device includes first memory cells of a first portion of pillar and second memory cells of a second portion of the pillar. When performing program operations based on consecutive addresses at a memory block selected from the memory blocks, the nonvolatile memory device sequentially completes first program operations of non-adjacent memory cells not adjacent to a boundary of the first portion and the second portion from among the first and second memory cells and then completes a second program operation of an adjacent memory cell adjacent to the boundary.

Abstract: A storage device includes a first nonvolatile memory chip; a second nonvolatile memory chip; and a controller. The controller may include a processor configured to execute a flash translation layer (FTL) loaded onto an on-chip memory; an ECC engine configured to generate first parity bits for data and to selectively generate second parity bits for the data, under control of the processor; and a nonvolatile memory interface circuit configured to transmit the data and the first parity bits to the first nonvolatile memory chip, and to selectively transmit the second parity bits selectively generated to the second nonvolatile memory chip.

Abstract: A method of accessing data in a storage device including first and second nonvolatile memories of different types is provided. The method includes setting a meta data attribute table by classifying a plurality of meta data based on a plurality of data attributes and accessible memory types, detecting a data attribute of first meta data among the plurality of meta data based on the meta data attribute table in response to receiving a first access request for the first meta data, determining a target memory optimized for the first meta data from among the first and second nonvolatile memories based on the detected data attribute of the first meta data, and performing an access operation on the target memory based on the first meta data. The plurality of meta data are used for controlling an operation of the storage device.

Abstract: Each of memory blocks of a nonvolatile memory device includes a memory cell region including first metal pads, first memory cells of a first portion of pillar, and second memory cells of a second portion of the pillar, and a peripheral circuit region including second metal pads, a row decoder, and a page buffer. When performing program operations based on consecutive addresses at a memory block selected from the memory blocks, the nonvolatile memory device sequentially completes first program operations of non-adjacent memory cells not adjacent to a boundary of the first portion and the second portion from among the first and second memory cells and then completes a second program operation of an adjacent memory cell adjacent to the boundary. The peripheral circuit region is vertically connected to the memory cell region by the first metal pads and the second metal pads directly.

Abstract: Each of memory blocks of a nonvolatile memory device includes first memory cells of a first portion of pillar and second memory cells of a second portion of the pillar. When performing program operations based on consecutive addresses at a memory block selected from the memory blocks, the nonvolatile memory device sequentially completes first program operations of non-adjacent memory cells not adjacent to a boundary of the first portion and the second portion from among the first and second memory cells and then completes a second program operation of an adjacent memory cell adjacent to the boundary.

Abstract: A method of accessing data in a storage device including first and second nonvolatile memories of different types is provided. The method includes setting a meta data attribute table by classifying a plurality of meta data based on a plurality of data attributes and accessible memory types, detecting a data attribute of first meta data among the plurality of meta data based on the meta data attribute table in response to receiving a first access request for the first meta data, determining a target memory optimized for the first meta data from among the first and second nonvolatile memories based on the detected data attribute of the first meta data, and performing an access operation on the target memory based on the first meta data. The plurality of meta data are used for controlling an operation of the storage device.

Abstract: A solid state drive and a method for accessing the metadata are provided. The solid state drive includes different kinds of first and second memories and a memory controller which controls the first and second memories, wherein the memory controller receives a metadata access request from a host, and includes a condition checker which determines conditions of the first and second memories in response to the metadata access request and selects at least one of the conditions, and the memory controller accesses to the memory selected by the condition checker.

Abstract: A semiconductor memory device is configured to perform a first verification operation by setting an initial voltage level of a verification voltage to a first voltage level and boosting the verification voltage during a first period. The semiconductor memory device includes a memory cell array that stores program data, a sensor generating sensing data, and a condition determination unit comparing the program data and the sensing data.

Abstract: A data storage device includes a nonvolatile memory having a plurality of first memory cells connected to a first word line and a plurality of second memory cells connected to a second word line. A memory controller divides first data to be programmed in the first memory cells into first and second data groups and divides second data to be programmed in the second memory cells into third and fourth data groups. The nonvolatile memory device performs a third program operation of the second data group and a fourth program operation of the fourth data group after sequentially performing a first program operation of the first data group and a second program operation of the third data group.

Abstract: A data storage device includes a nonvolatile memory having a plurality of first memory cells connected to a first word line and a plurality of second memory cells connected to a second word line. A memory controller divides first data to be programmed in the first memory cells into first and second data groups and divides second data to be programmed in the second memory cells into third and fourth data groups. The nonvolatile memory device performs a third program operation of the second data group and a fourth program operation of the fourth data group after sequentially performing a first program operation of the first data group and a second program operation of the third data group.

Abstract: A semiconductor memory device is configured to perform a first verification operation by setting an initial voltage level of a verification voltage to a first voltage level and boosting the verification voltage during a first period. The semiconductor memory device includes a memory cell array that stores program data, a sensor generating sensing data, and a condition determination unit comparing the program data and the sensing data.

Abstract: A negative voltage generator includes a direct current voltage generator configured to generate a direct current voltage, a reference voltage generator configured to generate a reference voltage, an oscillator configured to generate an oscillation clock, a charge pump configured to generate a negative voltage in response to a pump clock, and a voltage detector. The voltage detector is configured to detect the negative voltage by comparing a division voltage, obtained by voltage dividing the direct current voltage, with the reference voltage, and to generate the pump clock corresponding to the detected negative voltage based on the oscillation clock.

Abstract: A word line voltage generating method of a flash memory which includes generating a program voltage using a positive voltage generator; generating a plurality of negative program verification voltages corresponding to a plurality of negative data states using a negative voltage generator; and generating at least one or more program verification voltages corresponding to at least one or more states using the positive voltage generator. Generating a plurality of negative program verification voltages includes generating a first negative verification voltage; discharging an output of the negative voltage generator to become higher than the first negative verification voltage; and performing a negative charge pumping operation until an output of the negative voltage generator reaches a second negative verification voltage level.