Abstract: An electronic device includes: one or more processors; a memory storing instructions configured to cause the one or more processors to: install instrumentation points in respective tasks of an application, the instrumentation points including a source instrumentation point installed in a source task and a target instrumentation point installed in a target task, wherein the source task and the target task are configured to execute in parallel on the one or more processors, and wherein each task includes a respective sequence of instructions executable by the one or more processors, and determine a measure of a causal relationship between the source instrumentation point and the target instrumentation point based on observation of a delay in the target instrumentation point induced by a delay amount generated by the source instrumentation point.

Abstract: Disclosed is an apparatus and method for performing deep learning operations. The apparatus includes a systolic array comprising multiplier accumulator (MAC) units, and a control circuit configured to control an operation of a multiplexer connected to at least one of the MAC units and operations of the MAC units according to a plurality of operation modes.

Abstract: An accelerator, a method of operating the accelerator, and an electronic device including the accelerator. A method of operating the accelerator configured to perform a target operation includes packing input data with a data layout determined based on a word width of a memory in the accelerator and a spatial size of a filter to be applied to the target operation and storing the packed input data in the memory, and performing the target operation between a portion of the input data stored in a same word in the memory and weights of the filter.

Abstract: An accelerator, a method of operating the accelerator, and an electronic device including the accelerator. A method of operating the accelerator configured to perform a target operation includes packing input data with a data layout determined based on a word width of a memory in the accelerator and a spatial size of a filter to be applied to the target operation and storing the packed input data in the memory, and performing the target operation between a portion of the input data stored in a same word in the memory and weights of the filter.

Abstract: A computing method and device for large-scale computing is provided. The computing device includes at least one processing device configured to perform an operation related to a neural network, a sensor configured to sense an electrical characteristic of the at least one processing device, an operating frequency of the at least one processing device, and a temperature of the at least one processing device, and a processor configured to calculate a workload to be allocated to the at least one processing device based on an operating mode of the at least one processing device, the electrical characteristic of the at least one processing device, the operating frequency of the at least one processing device, and the temperature of the at least one processing device, and control the electrical characteristic, the operating frequency, and the temperature based on the operating mode and the workload.

Abstract: An apparatus with deep learning includes: a systolic adder tree including adder trees connected in row and column directions; and an input multiplexer connected to an input register of at least one of the adder trees and configured to determine column directional data movement between the adder trees based on operation modes.

Abstract: A computing device and method is disclosed. The computing device includes a plurality of processing cores, and a tile scheduler configured to update a cost matrix of each of the plurality of processing cores based on meta information of each of first tiles previously allocated to the plurality of processing cores and meta information of each of second tiles, and allocate the second tiles with respect to the plurality of processing cores using the updated cost matrix of each of the plurality of processing cores.

Abstract: An accelerator, a method of operating the accelerator, and an electronic device including the accelerator. A method of operating the accelerator configured to perform a target operation includes packing input data with a data layout determined based on a word width of a memory in the accelerator and a spatial size of a filter to be applied to the target operation and storing the packed input data in the memory, and performing the target operation between a portion of the input data stored in a same word in the memory and weights of the filter.

Abstract: Disclosed is an apparatus and method for performing deep learning operations. The apparatus includes a systolic array comprising multiplier accumulator (MAC) units, and a control circuit configured to control an operation of a multiplexer connected to at least one of the MAC units and operations of the MAC units according to a plurality of operation modes.