Patents by Inventor Jae-Eon Park
Jae-Eon Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240121543Abstract: An electronic device according to various embodiments of the present invention may comprise: a housing comprising a first surface facing in a first direction and a second surface facing in a second direction that is opposite to the first direction, the first surface comprising an at least partially transparent part and at least one opening formed adjacent to the at least partially transparent part; a camera positioned inside the housing, the camera comprising an image sensor facing in the first direction through the at least partially transparent part of the housing; and an acoustic component arranged between the first surface and the second surface, the acoustic component comprising a vibration plate configured to generate a sound such that the same moves in at least one direction selected from the first and second directions, a first passage formed in a third direction that is substantially perpendicular to the first direction such that the generated sound passes through the same, and a second passage formeType: ApplicationFiled: November 13, 2023Publication date: April 11, 2024Inventors: Young-Bae PARK, Byoung-Hee LEE, Jae-Hee YOU, Tae-Eon KIM, Han-Bom PARK, Sun-Young LEE, Byoung-Uk YOON, Kyung-Hee LEE, Ho-Chul HWANG
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Publication number: 20220364225Abstract: Provided is a method for forming a silicon oxycarbonitride film (SiOCN) with varying proportions of each element, using a disilane precursor under vapor deposition conditions, wherein the percent carbon incorporation into the SiOCN film may be varied between about 5 to about 60%, by utilizing co-reactants chosen from oxygen, ammonia, and nitrous oxide gas. The carbon-enriched SiOCN films thus formed may be converted to pure silicon dioxide films after an etch stop protocol by treatment with O2 plasma.Type: ApplicationFiled: June 30, 2022Publication date: November 17, 2022Inventors: Sungsil Cho, Seobong Chang, Jae Eon Park, Bryan C. Hendrix, Thomas H. Baum
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Patent number: 11414750Abstract: Provided is a method for forming a silicon oxycarbonitride film (SiOCN) with varying proportions of each element, using a disilane precursor under vapor deposition conditions, wherein the percent carbon incorporation into the SiOCN film may be varied between about 5 to about 60%, by utilizing co-reactants chosen from oxygen, ammonia, and nitrous oxide gas. The carbon-enriched SiOCN films thus formed may be converted to pure silicon dioxide films after an etch stop protocol by treatment with O2 plasma.Type: GrantFiled: May 7, 2020Date of Patent: August 16, 2022Assignee: ENTEGRIS, INC.Inventors: Sungsil Cho, Seobong Chang, Jae Eon Park, Bryan C. Hendrix, Thomas H. Baum
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Publication number: 20210395884Abstract: Provided are certain silicon precursor compounds which are useful in the formation of silicon-containing films in the manufacture of semiconductor devices, and more specifically to compositions and methods for forming such silicon-containing films, such as films comprising silicon dioxide or silicon nitride.Type: ApplicationFiled: June 23, 2021Publication date: December 23, 2021Inventors: Sungsil CHO, DaHye KIM, SooJin LEE, Jae Eon PARK, Bryan C. HENDRIX, Philip S.H. CHEN, Shawn D. NGUYEN
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Publication number: 20210301400Abstract: Provided are certain liquid silicon precursors useful for the deposition of silicon-containing films, such as films comprising silicon, silicon nitride, silicon oxynitride, silicon dioxide, silicon carbide, carbon-doped silicon nitride, or carbon-doped silicon oxynitride. Also provided are methods for forming such films utilizing vapor deposition techniques.Type: ApplicationFiled: March 26, 2021Publication date: September 30, 2021Inventors: SangJin LEE, DaHye KIM, Sungsil CHO, Seobong CHANG, Jae Eon PARK, Bryan C. HENDRIX, Thomas H. BAUM, SooJin LEE
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Publication number: 20210082708Abstract: The present disclosure relates to a bridging asymmetric haloalkynyl dicobalt hexacarbonyl precursors, and ultra high purity versions thereof, methods of making, and methods of using these bridging asymmetric haloalkynyl dicobalt hexacarbonyl precursors in a vapor deposition process. One aspect of the disclosure relates to an ultrahigh purity bridging asymmetric haloalkynyl dicobalt hexacarbonyl precursor of the formula Co2(CO)6(R3C?CR4), where R3 and R4 are different organic moieties and R4 is more electronegative or more electron withdrawing compared to R3.Type: ApplicationFiled: November 19, 2020Publication date: March 18, 2021Inventors: Sangbum HAN, Seobong CHANG, Bryan C. HENDRIX, Jae Eon PARK, Thomas H. BAUM
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Publication number: 20200354830Abstract: Provided is a method for forming a silicon oxycarbonitride film (SiOCN) with varying proportions of each element, using a disilane precursor under vapor deposition conditions, wherein the percent carbon incorporation into the SiOCN film may be varied between about 5 to about 60%, by utilizing co-reactants chosen from oxygen, ammonia, and nitrous oxide gas. The carbon-enriched SiOCN films thus formed may be converted to pure silicon dioxide films after an etch stop protocol by treatment with O2 plasma.Type: ApplicationFiled: May 7, 2020Publication date: November 12, 2020Inventors: Sungsil CHO, Seobong CHANG, Jae Eon PARK, Bryan C. HENDRIX, Thomas H. BAUM
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Patent number: 7838390Abstract: Methods of forming integrated circuit devices include forming a trench in a surface of semiconductor substrate and filling the trench with an electrically insulating region having a seam therein. The trench may be filled by depositing a sufficiently thick electrically insulating layer on sidewalls and a bottom of the trench. Curing ions are then implanted into the electrically insulating region at a sufficient energy and dose to reduce a degree of atomic order therein. The curing ions may be ones selected from a group consisting of nitrogen (N), phosphorus (P), boron (B), arsenic (As), carbon (C), argon (Ar), germanium (Ge), helium (He), neon (Ne) and xenon (Xe). These curing ions may be implanted at an energy of at least about 80 KeV and a dose of at least about 5×1014 ions/cm2. The electrically insulating region is then annealed at a sufficient temperature and for a sufficient duration to increase a degree of atomic order within the electrically insulating region.Type: GrantFiled: October 12, 2007Date of Patent: November 23, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-jung Kim, Joo-chan Kim, Jae-eon Park, Richard Anthony Conti, Zhao Lun, Johnny Widodo, William C. Wille, Biao Zuo
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Patent number: 7800134Abstract: Methods of forming CMOS integrated circuit devices include forming at least first, second and third transistors in a semiconductor substrate and then covering the transistors with one or more electrically insulating layers that impart a net stress (tensile or compressive) to channel regions of the transistors. The covering step may include covering the first and second transistors with a first electrically insulating layer having a sufficiently high internal stress characteristic to impart a net tensile (or compressive) stress in a channel region of the first transistor and covering the second and third transistors with a second electrically insulating layer having a sufficiently high internal stress characteristic to impart a net compressive (or tensile) stress in a channel region of the third transistor. A step may then performed to selectively remove a first portion of the second electrically insulating layer extending opposite a gate electrode of the second transistor.Type: GrantFiled: April 9, 2009Date of Patent: September 21, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Kyoung-woo Lee, Ja-hum Ku, Jae-eon Park
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Publication number: 20100029072Abstract: Methods of forming integrated circuit devices include forming an electrically insulating layer having a contact hole therein, on a substrate, and then depositing an electrically insulating liner onto a sidewall of the contact hole using an atomic layer deposition (ALD) technique. This electrically insulating liner, which may include gelatinous silica or silicon dioxide, for example, may be deposited to a thickness in a range from 40 ? to 100 ?. A portion of the electrically insulating liner is then removed from a bottom of the contact hole and a barrier metal layer is then formed on the electrically insulating liner and on a bottom of the contact hole. The step of forming the barrier metal layer may be followed by filling the contact hole with a metal interconnect.Type: ApplicationFiled: July 23, 2009Publication date: February 4, 2010Inventors: Jae-Eon Park, Jun-Keun Kwak, Jin-Woo Choi, Sunfei Fang, Jiang Yan
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Publication number: 20090194817Abstract: Methods of forming CMOS integrated circuit devices include forming at least first, second and third transistors in a semiconductor substrate and then covering the transistors with one or more electrically insulating layers that impart a net stress (tensile or compressive) to channel regions of the transistors. The covering step may include covering the first and second transistors with a first electrically insulating layer having a sufficiently high internal stress characteristic to impart a net tensile (or compressive) stress in a channel region of the first transistor and covering the second and third transistors with a second electrically insulating layer having a sufficiently high internal stress characteristic to impart a net compressive (or tensile) stress in a channel region of the third transistor. A step may then performed to selectively remove a first portion of the second electrically insulating layer extending opposite a gate electrode of the second transistor.Type: ApplicationFiled: April 9, 2009Publication date: August 6, 2009Inventors: Kyoung-woo Lee, Ja-hum Ku, Jae-eon Park
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Patent number: 7541288Abstract: Methods of forming integrated circuit devices include depositing an electrically insulating layer onto an integrated circuit substrate having integrated circuit structures thereon. This deposition step results in the formation of an electrically insulating layer having an undulating surface profile, which includes at least one peak and at least one valley adjacent to the at least one peak. A non-uniform thickening step is then performed. This non-uniform thickening step includes thickening a portion of the electrically insulating layer by redepositing portions of the electrically insulating layer from the least one peak to the at least one valley. This redeposition occurs using a sputter deposition technique that utilizes the electrically insulating layer as a sputter target.Type: GrantFiled: March 8, 2007Date of Patent: June 2, 2009Assignees: Samsung Electronics Co., Ltd., International Business Machines Corporation, Infineon Technologies AG, Chartered Semiconductor Manufacturing Ltd.Inventors: Jun-jung Kim, Ja-hum Ku, Jae-eon Park, Sunfei Fang, Alois Gutmann, O-sung Kwon, Johnny Widodo, Dae-won Yang
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Patent number: 7534678Abstract: Methods of forming CMOS integrated circuit devices include forming at least first, second and third transistors in a semiconductor substrate and then covering the transistors with one or more electrically insulating layers that impart a net stress (tensile or compressive) to channel regions of the transistors. The covering step may include covering the first and second transistors with a first electrically insulating layer having a sufficiently high internal stress characteristic to impart a net tensile (or compressive) stress in a channel region of the first transistor and covering the second and third transistors with a second electrically insulating layer having a sufficiently high internal stress characteristic to impart a net compressive (or tensile) stress in a channel region of the third transistor. A step may then performed to selectively remove a first portion of the second electrically insulating layer extending opposite a gate electrode of the second transistor.Type: GrantFiled: March 27, 2007Date of Patent: May 19, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Kyoung-woo Lee, Ja-hum Ku, Jae-eon Park
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Publication number: 20090098706Abstract: Methods of forming integrated circuit devices include forming a trench in a surface of semiconductor substrate and filling the trench with an electrically insulating region having a seam therein. The trench may be filled by depositing a sufficiently thick electrically insulating layer on sidewalls and a bottom of the trench. Curing ions are then implanted into the electrically insulating region at a sufficient energy and dose to reduce a degree of atomic order therein. The curing ions may be ones selected from a group consisting of nitrogen (N), phosphorus (P), boron (B), arsenic (As), carbon (C), argon (Ar), germanium (Ge), helium (He), neon (Ne) and xenon (Xe). These curing ions may be implanted at an energy of at least about 80 KeV and a dose of at least about 5×1014 ions/cm2. The electrically insulating region is then annealed at a sufficient temperature and for a sufficient duration to increase a degree of atomic order within the electrically insulating region.Type: ApplicationFiled: October 12, 2007Publication date: April 16, 2009Inventors: Jun-jung Kim, Joo-chan Kim, Jae-eon Park, Richard Anthony Conti, Zhao Lun, Johnny Widodo, William C. Wille, Biao Zuo
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Publication number: 20080242015Abstract: Methods of forming CMOS integrated circuit devices include forming at least first, second and third transistors in a semiconductor substrate and then covering the transistors with one or more electrically insulating layers that impart a net stress (tensile or compressive) to channel regions of the transistors. The covering step may include covering the first and second transistors with a first electrically insulating layer having a sufficiently high internal stress characteristic to impart a net tensile (or compressive) stress in a channel region of the first transistor and covering the second and third transistors with a second electrically insulating layer having a sufficiently high internal stress characteristic to impart a net compressive (or tensile) stress in a channel region of the third transistor. A step may then performed to selectively remove a first portion of the second electrically insulating layer extending opposite a gate electrode of the second transistor.Type: ApplicationFiled: March 27, 2007Publication date: October 2, 2008Inventors: Kyoung-woo Lee, Ja-hum Ku, Jae-eon Park
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Publication number: 20080220584Abstract: Methods of forming integrated circuit devices include depositing an electrically insulating layer onto an integrated circuit substrate having integrated circuit structures thereon. This deposition step results in the formation of an electrically insulating layer having an undulating surface profile, which includes at least one peak and at least on valley adjacent to the at least one peak. A non-uniform thickening step is then performed. This non-uniform thickening step includes thickening a portion of the electrically insulating layer by redepositing portions of the electrically insulating layer from the least one peak to the at least one valley. This redeposition occurs using a sputter deposition technique that utilizes the electrically insulating layer as a sputter target.Type: ApplicationFiled: March 8, 2007Publication date: September 11, 2008Inventors: Jun-jung Kim, Ja-hum Ku, Jae-eon Park, Sunfei Fang, Alois Gutmann, O-sung Kwon, Johnny Widodo, Dae-won Yang
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Publication number: 20080124859Abstract: Methods of forming field effect transistors include methods of forming PMOS and NMOS transistors by forming first and second gate electrodes on a substrate and then forming an electrically insulating layer having etch-enhancing impurities therein, on the first and second gate electrodes. The electrically insulating layer may be formed as a boron-doped silicon nitride layer or an electrically insulating layer that is doped with germanium and/or fluorine. The electrically insulating layer is etched-back to define first sidewall spacers on the first gate electrode and second sidewall spacers on the second gate electrode. P-type source and drain region dopants are then implanted into the semiconductor substrate, using the first sidewall spacers as a first implant mask. The second sidewall spacers on the second gate electrode are then etched back to reduce their lateral dimensions.Type: ApplicationFiled: November 27, 2006Publication date: May 29, 2008Inventors: Min Chul Sun, Jong Ho Yang, Young Gun Ko, Ja Hum Ku, Jae Eon Park, Jeong Hwan Yang, Christopher Vincent Baiocco, Gerald Leake
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Publication number: 20080029823Abstract: In a semiconductor device having a dual stress liner for improving electron mobility, the dual stress liner includes a first liner portion formed on a PMOSFET and a second liner portion formed on an NMOSFET. The first liner portion has a first compressive stress, and the second liner portion has a second compressive stress smaller than the first compressive stress. The dual stress liner may be formed by forming a stress liner on a semiconductor substrate on which the PMOSFET and the NMOSFET are formed and selectively exposing a portion of the stress liner on the NMOSFET.Type: ApplicationFiled: October 11, 2007Publication date: February 7, 2008Inventors: Jae-Eon Park, Ja-Hum Ku, Jun-Jung Kim, Dae-Kwon Kang, Young Teh
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Patent number: 7323419Abstract: A method of fabricating a semiconductor device including a high-k dielectric for as a gate insulating layer is provided. The method includes forming a high-k dielectric layer and a conductive layer on a substrate, dry etching a portion of the conductive layer, performing a process to increase a wet etch rate of a remaining portion of the conductive layer, and forming a conductive layer pattern by wet etching the remaining portion of the conductive layer after performing the plasma process or the ion implantation. The process to increase the wet etch rate of the conductive layer including a plasma process and/or an ion implantation on the remaining portion of the conductive layer.Type: GrantFiled: January 25, 2006Date of Patent: January 29, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Hyung-suk Jung, Jong-ho Lee, Jae-eon Park, Sung-kee Han, Min-joo Kim
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Patent number: 7297584Abstract: In a semiconductor device having a dual stress liner for improving electron mobility, the dual stress liner includes a first liner portion formed on a PMOSFET and a second liner portion formed on an NMOSFET. The first liner portion has a first compressive stress, and the second liner portion has a second compressive stress smaller than the first compressive stress. The dual stress liner may be formed by forming a stress liner on a semiconductor substrate on which the PMOSFET and the NMOSFET are formed and selectively exposing a portion of the stress liner on the NMOSFET.Type: GrantFiled: October 7, 2005Date of Patent: November 20, 2007Assignees: Samsung Electronics Co., Ltd., Chartered Semiconductor Manufacturing, Ltd.Inventors: Jae-Eon Park, Ja-Hum Ku, Jun-Jung Kim, Dae-Kwon Kang, Young Way Teh