Abstract: A semiconductor memory device includes a plurality of bit lines disposed over memory cells along a second direction intersecting with a first direction, and extending in the first direction; and a plurality of s first wirings and a plurality of second wirings alternately disposed along the second direction over the bit lines, and extending in the first direction while being bent into zigzag shapes.

Abstract: A semiconductor memory device includes a plurality of bit lines disposed over memory cells along a second direction intersecting with a first direction, and extending in the first direction; and a plurality of first wirings and a plurality of second wirings alternately disposed along the second direction over the bit lines, and extending in the first direction while being bent into zigzag shapes.

Abstract: Provided herein is a semiconductor memory device including: a memory cell array having a multilayer stacked structure; and a peripheral circuit configured to drive the memory cell array. The peripheral circuit includes a power decoupling capacitor circuit configured to provide decoupling capacitors to the memory cell array and the peripheral circuit. The power decoupling capacitor circuit includes conductive lines which are alternately stacked on top of one another, a plurality of semiconductor pillars configured to pass through the conductive lines, a horizontal connector configured to connect the semiconductor pillars to each other, and a vertical connector configured to pass through the conductive lines and insulated from the horizontal connector.

Abstract: Provided herein is a semiconductor memory device including: a memory cell array having a multilayer stacked structure; and a peripheral circuit configured to drive the memory cell array. The peripheral circuit includes a power decoupling capacitor circuit configured to provide decoupling capacitors to the memory cell array and the peripheral circuit. The power decoupling capacitor circuit includes conductive lines which are alternately stacked on top of one another, a plurality of semiconductor pillars configured to pass through the conductive lines, a horizontal connector configured to connect the semiconductor pillars to each other, and a vertical connector configured to pass through the conductive lines and insulated from the horizontal connector.

Abstract: A semiconductor device and a method of fabricating the same are disclosed. The semiconductor device includes: a memory cell structure formed over a semiconductor substrate; a channel portion formed in the semiconductor substrate; a through-hole formed to pass through the memory cell structure; a first channel region formed over sidewalls of the through-hole; and a second channel region formed at a center part of the through-hole, and spaced apart from the first channel region, wherein each of the first channel region and the second channel region is coupled to the channel portion.

Abstract: A nonvolatile memory device includes a source line having a shape of a three-dimensional (3D) cap. The nonvolatile memory device includes a first vertical channel and a second vertical channel, a source contact disposed over the first vertical channel, a drain contact disposed over the second vertical channel, a source-line barrier disposed between the source contact and the drain contact, and a source-line plate coupling the source contact and the source-line barrier.

Abstract: A semiconductor device and a method of fabricating the same are disclosed. The semiconductor device includes: a memory cell structure formed over a semiconductor substrate; a channel portion formed in the semiconductor substrate; a through-hole formed to pass through the memory cell structure; a first channel region formed over sidewalls of the through-hole; and a second channel region formed at a center part of the through-hole, and spaced apart from the first channel region, wherein each of the first channel region and the second channel region is coupled to the channel portion.

Abstract: A nonvolatile memory device includes a source line having a shape of a three-dimensional (3D) cap. The nonvolatile memory device includes a first vertical channel and a second vertical channel, a source contact disposed over the first vertical channel, a drain contact disposed over the second vertical channel, a source-line barrier disposed between the source contact and the drain contact, and a source-line plate coupling the source contact and the source-line barrier.

Abstract: A semiconductor device is provided having an electrostatic discharge (ESD) protection function. It includes a plurality of no-connection (NC) pads, each associated with a corresponding NC ball, and each connected to a corresponding internal circuit, an ESD protection circuit connected to each one of the plurality of NC pads, and a fuse located between each respective NC pad and its corresponding internal circuit.