Patents by Inventor Jae-Eun Lim

Jae-Eun Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7902628
    Abstract: The present invention relates to a semiconductor device with a device isolation structure and a method for fabricating the same. The semiconductor device includes: a substrate provided with a trench formed in the substrate; and at least one device isolation structure including an oxide layer formed on the trench, a nitride layer formed on the oxide layer disposed on sidewalls of the trench and a high density plasma oxide layer formed on the nitride layer to fill the trench.
    Type: Grant
    Filed: April 6, 2009
    Date of Patent: March 8, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jae-Eun Lim, Sun-Hwan Hwang
  • Publication number: 20090189243
    Abstract: The present invention relates to a semiconductor device with a device isolation structure and a method for fabricating the same. The semiconductor device includes: a substrate provided with a trench formed in the substrate; and at least one device isolation structure including an oxide layer formed on the trench, a nitride layer formed on the oxide layer disposed on sidewalls of the trench and a high density plasma oxide layer formed on the nitride layer to fill the trench.
    Type: Application
    Filed: April 6, 2009
    Publication date: July 30, 2009
    Inventors: Jae-Eun Lim, Sun-Hwan Hwang
  • Patent number: 7528052
    Abstract: The present invention relates to a semiconductor device with a device isolation structure and a method for fabricating the same. The semiconductor device includes: a substrate provided with a trench formed in the substrate; and at least one device isolation structure including an oxide layer formed on the trench, a nitride layer formed on the oxide layer disposed on sidewalls of the trench and a high density plasma oxide layer formed on the nitride layer to fill the trench.
    Type: Grant
    Filed: August 27, 2004
    Date of Patent: May 5, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jae-Eun Lim, Sun-Hwan Hwang
  • Patent number: 6953734
    Abstract: The method for manufacturing an STI in a semiconductor device with an enhanced gap-fill property and leakage property is disclosed by introducing a nitridation process instead of forming a liner nitride. The method includes steps of: preparing a semiconductor substrate obtained by a predetermined process on which a pad oxide and a pad nitride are formed on predetermined locations thereof; forming an isolation trench with a predetermined depth in the semiconductor substrate; forming a wall oxide on the trench; forming a liner oxide on the wall oxide and an exposed surface of the pad nitride; carrying out a nitridation process for forming a nitrided oxide; forming an insulating layer over the resultant structure, wherein the isolation trench is filled with the insulating layer; and planarizing a top face of the insulating layer.
    Type: Grant
    Filed: December 16, 2003
    Date of Patent: October 11, 2005
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jae-Eun Lim, Yong-Sun Sohn
  • Publication number: 20050116312
    Abstract: The present invention relates to a semiconductor device with a device isolation structure and a method for fabricating the same. The semiconductor device includes: a substrate provided with a trench formed in the substrate; and at least one device isolation structure including an oxide layer formed on the trench, a nitride layer formed on the oxide layer disposed on sidewalls of the trench and a high density plasma oxide layer formed on the nitride layer to fill the trench.
    Type: Application
    Filed: August 27, 2004
    Publication date: June 2, 2005
    Inventors: Jae-Eun Lim, Sun-Hwan Hwang
  • Publication number: 20050112841
    Abstract: Disclosed is a method for isolating semiconductor devices. The method includes the steps of: forming a semi-finished substrate provided with a trench and a patterned pad nitride layer on a substrate; forming a first oxide layer on at least one portion of the trench; forming a second oxide layer on the first oxide layer and the patterned pad nitride layer; forming a nitride layer on the second oxide layer; forming an isolation oxide layer on the second oxide layer; and etching the isolation oxide layer, wherein the second oxide layer serves as an etch stop for the nitride layer.
    Type: Application
    Filed: June 22, 2004
    Publication date: May 26, 2005
    Inventor: Jae-Eun Lim
  • Publication number: 20050020027
    Abstract: The method for manufacturing an STI in a semiconductor device with an enhanced gap-fill property and leakage property is disclosed by introducing a nitridation process instead of forming a liner nitride. The method includes steps of: preparing a semiconductor substrate obtained by a predetermined process on which a pad oxide and a pad nitride are formed on predetermined locations thereof; forming an isolation trench with a predetermined depth in the semiconductor substrate; forming a wall oxide on the trench; forming a liner oxide on the wall oxide and an exposed surface of the pad nitride; carrying out a nitridation process for forming a nitrided oxide; forming an insulating layer over the resultant structure, wherein the isolation trench is filled with the insulating layer; and planarizing a top face of the insulating layer.
    Type: Application
    Filed: December 16, 2003
    Publication date: January 27, 2005
    Inventors: Jae-Eun Lim, Yong-Sun Sohn