Patents by Inventor Jae-Geun Oh

Jae-Geun Oh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240124048
    Abstract: The present invention provides an electric independent steering apparatus comprising: a first knuckle having one end coupled to the lower end of a strut part, and including an upper support part extending and protruding outwardly from the one end and a lower support part extending and protruding from the other end so as to face the upper support part; a second knuckle which is rotatably disposed on the lower support part inside the first knuckle, has a motor installed therein, and has a driving wheel coupled to the outside thereof; and a harmonic gear which is disposed so as to be rotatable from the upper support part and relatively rotates from the first knuckle together with the second knuckle.
    Type: Application
    Filed: January 21, 2022
    Publication date: April 18, 2024
    Applicants: Seohan Innobility Co., Ltd., Korea Movenex Co., Ltd.
    Inventors: Byung Ki OH, Jae Geun BANG
  • Patent number: 11963467
    Abstract: An electronic device includes a semiconductor memory. A method for fabricating the electronic device includes forming a first memory cell extending vertically from a surface of substrate and having a first upper portion that protrudes laterally, forming a second memory cell extending vertically from the surface of the substrate and having a second upper portion that protrudes laterally towards the first upper portion, and forming a liner layer over the first and second memory cells, the liner layer having a first portion disposed over the first upper portion and a second portion disposed over the second upper portion, the first and second portions of the liner layer contacting each other.
    Type: Grant
    Filed: May 13, 2022
    Date of Patent: April 16, 2024
    Assignee: SK hynix Inc.
    Inventors: Hyo-June Kim, Hyun-Seok Kang, Chi-Ho Kim, Jae-Geun Oh
  • Patent number: 11952055
    Abstract: The present invention provides an electric independent steering apparatus comprising: a first knuckle having one end coupled to the lower end of a strut part, and including an upper support part extending and protruding outwardly from the one end and a lower support part extending and protruding from the other end so as to face the upper support part; a second knuckle which is rotatably disposed on the lower support part inside the first knuckle, has a motor installed therein, and has a driving wheel coupled to the outside thereof; and a harmonic gear which is disposed so as to be rotatable from the upper support part and relatively rotates from the first knuckle together with the second knuckle.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: April 9, 2024
    Assignees: Seohan Innobility Co., Ltd., Korea Movenex Co., Ltd.
    Inventors: Byung Ki Oh, Jae Geun Bang
  • Publication number: 20220278275
    Abstract: An electronic device includes a semiconductor memory. A method for fabricating the electronic device includes forming a first memory cell extending vertically from a surface of substrate and having a first upper portion that protrudes laterally, forming a second memory cell extending vertically from the surface of the substrate and having a second upper portion that protrudes laterally towards the first upper portion, and forming a liner layer over the first and second memory cells, the liner layer having a first portion disposed over the first upper portion and a second portion disposed over the second upper portion, the first and second portions of the liner layer contacting each other.
    Type: Application
    Filed: May 13, 2022
    Publication date: September 1, 2022
    Inventors: Hyo-June KIM, Hyun-Seok KANG, Chi-Ho KIM, Jae-Geun OH
  • Patent number: 11362273
    Abstract: An electronic device includes a semiconductor memory. A method for fabricating the electronic device includes forming a first memory cell extending vertically from a surface of substrate and having a first upper portion that protrudes laterally, forming a second memory cell extending vertically from the surface of the substrate and having a second upper portion that protrudes laterally towards the first upper portion, and forming a liner layer over the first and second memory cells, the liner layer having a first portion disposed over the first upper portion and a second portion disposed over the second upper portion, the first and second portions of the liner layer contacting each other.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: June 14, 2022
    Assignee: SK hynix Inc.
    Inventors: Hyo-June Kim, Hyun-Seok Kang, Chi-Ho Kim, Jae-Geun Oh
  • Patent number: 11271039
    Abstract: This technology provides an electronic device and a method for fabricating the same. An electronic device in accordance with an implementation of this document may include a substrate including a first portion in a first region and a second portion in a second region; a plurality of memory cells disposed over the first portion of the substrate; a first insulating layer extending over the second portion of the substrate and at least partially filling a space between adjacent ones of the plurality of memory cells; and a second insulating layer disposed over the first insulating layer. The first insulating layer has a dielectric constant smaller than that of the second insulating layer, a thermal conductivity smaller than that of the second insulating layer, or both.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: March 8, 2022
    Assignee: SK hynix Inc.
    Inventors: Chi-Ho Kim, Min-Seon Kang, Hyun-Seok Kang, Hyo-June Kim, Jae-Geun Oh, Su-Jin Chae
  • Patent number: 11189630
    Abstract: A memory device and an electronic device including the same are provided. The memory device includes a first memory cell disposed at an intersection of first and second conductive lines that extend in first and second directions, respectively, a second memory cell spaced apart from the first memory cell by a first distance in the first direction, a third memory cell spaced apart from the first memory cell by a second distance in the second direction, a first insulating pattern disposed between the first memory cell and the second memory cell, and a second insulating pattern disposed between the first memory cell and the third memory cell. The second insulating pattern has a lower thermal conductivity than the first insulating pattern.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: November 30, 2021
    Assignee: SK hynix Inc.
    Inventors: Dae Gun Kang, Hyun Seok Kang, Deok Lae Ahn, Jae Geun Oh, Won Ki Joo, Su-Jin Chae
  • Publication number: 20200373353
    Abstract: This technology provides an electronic device and a method for fabricating the same. An electronic device in accordance with an implementation of this document may include a substrate including a first portion in a first region and a second portion in a second region; a plurality of memory cells disposed over the first portion of the substrate; a first insulating layer extending over the second portion of the substrate and at least partially filling a space between adjacent ones of the plurality of memory cells; and a second insulating layer disposed over the first insulating layer. The first insulating layer has a dielectric constant smaller than that of the second insulating layer, a thermal conductivity smaller than that of the second insulating layer, or both.
    Type: Application
    Filed: December 11, 2019
    Publication date: November 26, 2020
    Inventors: Chi-Ho KIM, Min-Seon KANG, Hyun-Seok KANG, Hyo-June KIM, Jae-Geun OH, Su-Jin CHAE
  • Publication number: 20200287131
    Abstract: An electronic device includes a semiconductor memory. A method for fabricating the electronic device includes forming a first memory cell extending vertically from a surface of substrate and having a first upper portion that protrudes laterally, forming a second memory cell extending vertically from the surface of the substrate and having a second upper portion that protrudes laterally towards the first upper portion, and forming a liner layer over the first and second memory cells, the liner layer having a first portion disposed over the first upper portion and a second portion disposed over the second upper portion, the first and second portions of the liner layer contacting each other.
    Type: Application
    Filed: October 22, 2019
    Publication date: September 10, 2020
    Inventors: Hyo-June KIM, Hyun-Seok KANG, Chi-Ho KIM, Jae-Geun OH
  • Publication number: 20200203361
    Abstract: A memory device and an electronic device including the same are provided. The memory device includes a first memory cell disposed at an intersection of first and second conductive lines that extend in first and second directions, respectively, a second memory cell spaced apart from the first memory cell by a first distance in the first direction, a third memory cell spaced apart from the first memory cell by a second distance in the second direction, a first insulating pattern disposed between the first memory cell and the second memory cell, and a second insulating pattern disposed between the first memory cell and the third memory cell. The second insulating pattern has a lower thermal conductivity than the first insulating pattern.
    Type: Application
    Filed: August 27, 2019
    Publication date: June 25, 2020
    Inventors: Dae Gun KANG, Hyun Seok KANG, Deok Lae AHN, Jae Geun OH, Won Ki JOO, Su-Jin CHAE
  • Patent number: 9972384
    Abstract: An electronic device comprising a semiconductor memory unit that includes a resistance variable element formed over a substrate, and including stacked therein a bottom electrode, a variable resistance layer and a top electrode, and a barrier layer formed over the resistance variable element, and including an amorphous silicon layer which is doped with at least one kind of impurity.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: May 15, 2018
    Assignee: SK hynix Inc.
    Inventors: Sook-Joo Kim, Jae-Geun Oh, Keum-Bum Lee, Hyung-Suk Lee
  • Patent number: 9799704
    Abstract: An electronic device with improved variable resistance characteristics and a method for fabricating the same are provided. In an embodiment of the disclosed technology, a method for forming an electronic device with a semiconductor memory includes forming a crystalized doped layer over a substrate; forming a barrier layer over the doped layer; forming a metal layer over the barrier layer; and reacting the barrier layer with a portion of the metal layer. The electronic device and the method of fabricating the same according to embodiments of the disclosed technology may have improved variable resistance characteristics.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: October 24, 2017
    Assignee: SK hynix Inc.
    Inventors: Sook-Joo Kim, Jae-Geun Oh, Hyung-Suk Lee
  • Publication number: 20170221557
    Abstract: An electronic device comprising a semiconductor memory unit that includes a resistance variable element formed over a substrate, and including stacked therein a bottom electrode, a variable resistance layer and a top electrode, and a barrier layer formed over the resistance variable element, and including an amorphous silicon layer which is doped with at least one kind of impurity.
    Type: Application
    Filed: April 14, 2017
    Publication date: August 3, 2017
    Inventors: Sook-Joo Kim, Jae-Geun Oh, Keum-Bum Lee, Hyung-Suk Lee
  • Patent number: 9627616
    Abstract: An electronic device comprising a semiconductor memory unit that includes a resistance variable element formed over a substrate, and including stacked therein a bottom electrode, a variable resistance layer and a top electrode, and a barrier layer formed over the resistance variable element, and including an amorphous silicon layer which is doped with at least one kind of impurity.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: April 18, 2017
    Assignee: SK hynix Inc.
    Inventors: Sook-Joo Kim, Jae-Geun Oh, Keum-Bum Lee, Hyung-Suk Lee
  • Publication number: 20160358975
    Abstract: An electronic device with improved variable resistance characteristics and a method for fabricating the same are provided. In an embodiment of the disclosed technology, a method for forming an electronic device with a semiconductor memory includes forming a crystalized doped layer over a substrate; forming a barrier layer over the doped layer; forming a metal layer over the barrier layer; and reacting the barrier layer with a portion of the metal layer. The electronic device and the method of fabricating the same according to embodiments of the disclosed technology may have improved variable resistance characteristics.
    Type: Application
    Filed: August 15, 2016
    Publication date: December 8, 2016
    Inventors: Sook-Joo Kim, Jae-Geun Oh, Hyung-Suk Lee
  • Patent number: 9418838
    Abstract: An electronic device with improved variable resistance characteristics and a method for fabricating the same are provided. In an embodiment of the disclosed technology, a method for forming an electronic device with a semiconductor memory includes forming a crystalized doped layer over a substrate; forming a barrier layer over the doped layer; forming a metal layer over the barrier layer; and reacting the barrier layer with a portion of the metal layer. The electronic device and the method of fabricating the same according to embodiments of the disclosed technology may have improved variable resistance characteristics.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: August 16, 2016
    Assignee: SK hynix Inc.
    Inventors: Sook-Joo Kim, Jae-Geun Oh, Hyung-Suk Lee
  • Patent number: 9406871
    Abstract: According to one embodiment, a magnetoresistive element is disclosed. The magnetoresistive element includes a reference layer, a tunnel barrier layer, a storage layer. The storage layer includes a first region and a second region provided outside the first region to surround the first region, the second region including element included in the first region and another element being different from the element. The magnetoresistive element further includes a cap layer including a third region and a fourth region provided outside the third region to surround the third region, the fourth region including an element included in the third region and the another element.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: August 2, 2016
    Assignees: KABUSHIKI KAISHA TOSHIBA, SK HYNIX INC.
    Inventors: Masahiko Nakayama, Masatoshi Yoshikawa, Tadashi Kai, Yutaka Hashimoto, Masaru Toko, Hiroaki Yoda, Jae Geun Oh, Keum Bum Lee, Choon Kun Ryu, Hyung Suk Lee, Sook Joo Kim
  • Patent number: 9385304
    Abstract: According to one embodiment, a magnetic memory is disclosed. The memory includes a conductive layer containing a first metal material, a stacked body above the conductive layer, and including a first magnetization film containing a second metal material, a second magnetization film, and a tunnel barrier layer between the first magnetization film and the second magnetization film, and an insulating layer on a side face of the stacked body, and containing an oxide of the first metal material. The first magnetization film and/or the second magnetization film includes a first region positioned in a central portion, and a second region positioned in an edge portion and containing As, P, Ge, Ga, Sb, In, N, Ar, He, F, Cl, Br, I, Si, B, C, O, Zr, Tb, S, Se, or Ti.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: July 5, 2016
    Assignees: KABUSHIKI KAISHA TOSHIBA, SK HYNIX INC.
    Inventors: Masahiko Nakayama, Tadashi Kai, Masaru Toko, Hiroaki Yoda, Hyung Suk Lee, Jae Geun Oh, Choon Kun Ryu, Min Suk Lee
  • Publication number: 20160181522
    Abstract: An electronic device with improved variable resistance characteristics and a method for fabricating the same are provided. In an embodiment of the disclosed technology, a method for forming an electronic device with a semiconductor memory includes forming a crystalized doped layer over a substrate; forming a barrier layer over the doped layer; forming a metal layer over the barrier layer; and reacting the barrier layer with a portion of the metal layer. The electronic device and the method of fabricating the same according to embodiments of the disclosed technology may have improved variable resistance characteristics.
    Type: Application
    Filed: July 6, 2015
    Publication date: June 23, 2016
    Inventors: Sook-Joo Kim, Jae-Geun Oh, Hyung-Suk Lee
  • Publication number: 20160149121
    Abstract: This technology provides an electronic device and method for fabricating the same. A method for fabricating an electronic device comprising a transistor includes forming a junction region which is partially amorphized in the semiconductor substrate at a side of the gate; forming a metal layer over the junction region; and performing a heat treatment process on the metal layer into a metal-semiconductor compound layer while crystallizing the junction region.
    Type: Application
    Filed: July 1, 2015
    Publication date: May 26, 2016
    Inventors: Jae-Geun Oh, Choon-Kun Ryu, Hyung-Suk Lee