Abstract: Provided are a silicon nitride film etching composition, a method of etching a silicon nitride film using the same, and a manufacturing method of a semiconductor device. Specifically, a silicon nitride film may be stably etched with a high selection ratio relative to a silicon oxide film, and when the composition is applied to an etching process at a high temperature and a semiconductor manufacturing process, not only no precipitate occurs but also anomalous growth in which the thickness of the silicon oxide film is rather increased does not occur, thereby minimizing defects and reliability reduction.

Abstract: A memory system including a memory controller with channel interfaces connecting memory groups via channels. Each channel interface communicates control, address and/or data (CAD) signals to a channel-connected memory group synchronously with a slave clock derived from an input clock. The various slave clocks being uniquely generated by application of channel interface specific phase/frequency modulation or temporal delay, such that the respective CAD signals are characterized by skewed transition timing.

Abstract: A storage device set includes a storage device configured to communicate with a host, the storage device including a controller configured to generate encrypted input data by encrypting data; and a reconfigurable logic chip configured to receive the encrypted input data from the storage device, generate processed data by processing the encrypted input data according to a configuration, and generate encrypted output data by encrypting the processed data.

Abstract: A storage device set includes a storage device configured to communicate with a host, the storage device including a controller configured to generate encrypted input data by encrypting data; and a reconfigurable logic chip configured to receive the encrypted input data from the storage device, generate processed data by processing the encrypted input data according to a configuration, and generate encrypted output data by encrypting the processed data.

Abstract: A memory system including a memory controller with channel interfaces connecting memory groups via channels. Each channel interface communicates control, address and/or data (CAD) signals to a channel-connected memory group synchronously with a slave clock derived from an input clock. The various slave clocks being uniquely generated by application of channel interface specific phase/frequency modulation or temporal delay, such that the respective CAD signals are characterized by skewed transition timing.

Abstract: A memory system including a memory controller with channel interfaces connecting memory groups via channels. Each channel interface communicates control, address and/or data (CAD) signals to a channel-connected memory group synchronously with a slave clock derived from an input clock. The various slave clocks being uniquely generated by application of channel interface specific phase/frequency modulation or temporal delay, such that the respective CAD signals are characterized by skewed transition timing.

Abstract: A storage device set includes a storage device configured to communicate with a host, the storage device including a controller configured to generate encrypted input data by encrypting data; and a reconfigurable logic chip configured to receive the encrypted input data from the storage device, generate processed data by processing the encrypted input data according to a configuration, and generate encrypted output data by encrypting the processed data.

Abstract: Provided is a storage device set. The storage device set includes a storage device configured to communicate with a host, the storage device including a controller configured to generate encrypted input data by encrypting data; and a reconfigurable logic chip configured to receive the encrypted input data from the storage device, generate processed data by processing the encrypted input data according to a configuration, and generate encrypted output data by encrypting the processed data.

Abstract: A method of interfacing a memory controller and a memory device in a memory system includes transmitting a control signal between the memory controller and the memory device using a time division multiplexing (TDM) communication process, and transmitting data between the memory controller and the memory device using a serializer/deserializer (SERDES) communication process. Data communication in the memory system is performed via a physical channel and a plurality of virtual channels corresponding to the physical channel.

Abstract: Provided is a storage device set. The storage device set includes a storage device configured to communicate with a host, the storage device including a controller configured to generate encrypted input data by encrypting data; and a reconfigurable logic chip configured to receive the encrypted input data from the storage device, generate processed data by processing the encrypted input data according to a configuration, and generate encrypted output data by encrypting the processed data.

Abstract: A method of operating a memory controller is provided. The method of operating a memory controller according to an exemplary embodiment of the present inventive concepts includes sequentially receiving, by the memory controller, first data segments each having a first size from a host, sequentially storing, by the memory controller, the first data segments in the buffer until a sum of sizes of changed data among data stored in a buffer included in the memory controller is a second size, and programming, by the memory controller, the changed data having the second size in a memory space of a non-volatile memory as a second data segment.

Abstract: A memory system including a memory controller with channel interfaces connecting memory groups via channels. Each channel interface communicates control, address and/or data (CAD) signals to a channel-connected memory group synchronously with a slave clock derived from an input clock. The various slave clocks being uniquely generated by application of channel interface specific phase/frequency modulation or temporal delay, such that the respective CAD signals are characterized by skewed transition timing.

Abstract: A memory system including a memory controller with channel interfaces connecting memory groups via channels. Each channel interface communicates control, address and/or data (CAD) signals to a channel-connected memory group synchronously with a slave clock derived from an input clock. The various slave clocks being uniquely generated by application of channel interface specific phase/frequency modulation or temporal delay, such that the respective CAD signals are characterized by skewed transition timing.

Abstract: A method of operating a memory controller is provided. The method of operating a memory controller according to an exemplary embodiment of the present inventive concepts includes sequentially receiving, by the memory controller, first data segments each having a first size from a host, sequentially storing, by the memory controller, the first data segments in the buffer until a sum of sizes of changed data among data stored in a buffer included in the memory controller is a second size, and programming, by the memory controller, the changed data having the second size in a memory space of a non-volatile memory as a second data segment.

Abstract: A method of operating a memory controller includes allocating a new entry whenever a write command is input from a host; and transferring data corresponding to an entry in a specific state among a plurality of states to the host in response to a read command output from the host, wherein the plurality of states are a FREE state, a WRITE state, a WRITE OLD state, a READ state, a PEND state, a PEND OLD state, a CACHE state, and a DEL state, and the specific state is at least one of the PEND state, the PEND OLD state, or the CACHE state.

Abstract: A memory system including a memory controller with channel interfaces connecting memory groups via channels. Each channel interface communicates control, address and/or data (CAD) signals to a channel-connected memory group synchronously with a slave clock derived from an input clock. The various slave clocks being uniquely generated by application of channel interface specific phase/frequency modulation or temporal delay, such that the respective CAD signals are characterized by skewed transition timing.

Abstract: A method of operating a memory controller includes allocating a new entry whenever a write command is input from a host; and transferring data corresponding to an entry in a specific state among a plurality of states to the host in response to a read command output from the host, wherein the plurality of states are a FREE state, a WRITE state, a WRITE OLD state, a READ state, a PEND state, a PEND OLD state, a CACHE state, and a DEL state, and the specific state is at least one of the PEND state, the PEND OLD state, or the CACHE state.

Abstract: A method of interfacing a memory controller and a memory device in a memory system includes transmitting a control signal between the memory controller and the memory device using a time division multiplexing (TDM) communication process, and transmitting data between the memory controller and the memory device using a serializer/deserializer (SERDES) communication process. Data communication in the memory system is performed via a physical channel and a plurality of virtual channels corresponding to the physical channel.

Abstract: Performing a write operation or a read operation in a memory system may include compressing data of a first size unit, generating a plurality of types of Error Checking and Correction (ECC) information based on the compressed data, combining the compressed data and the plurality of types of ECC information in units of a second size, and writing the information combined in units of the second size into a memory device.

Abstract: Disclosed is a thermorod capable of actively releasing drugs according to temperature of the thermorod and a method of manufacturing the same. The thermorod generates heat by eddy current loss and hysteresis loss in an induced magnetic field. The thermorods can effectively administer drugs, such as anti-cancer drugs, since the thermorods may be used to perform local hyperthermia at 36.5° C. or above and to actively control the active drug release and delivery according to temperature as well. The thermorods may be useful in the treatment of resting tumor cells along with hyperthermia by performing a surgical operation on lesion sites of biological tissues. Using the thermorod, the drug is effectively delivered to an affected part in response to the active drug release. This can minimize the toxicity caused by an increase in blood drug concentration, which occurs when a drug is administered by a conventional method.