Abstract: An oil drain structure of a valve timing adjusting device for an internal combustion engine is provided to adjust a valve timing of at least one of an intake valve and an exhaust valve by a torque of a cam shaft and a pressure of a working fluid. The oil drain structure of the valve timing adjusting device includes a rotation preventing means to suppress a position change between a rotor and a housing by regulating a relative rotation of the rotor with respect to the housing.

Abstract: A storage device includes a storage device communicably connected to a host; a nonvolatile memory configured to store calibration data of the host; and a calibration circuit configured to receive a descriptor from the host including the setting information and update the calibration data with the received setting information.

Abstract: An oil drain structure of a valve timing adjusting device for an internal combustion engine is provided to adjust a valve timing of at least one of an intake valve and an exhaust valve by a torque of a cam shaft and a pressure of a working fluid. The oil drain structure of the valve timing adjusting device includes a rotation preventing means to suppress a position change between a rotor and a housing by regulating a relative rotation of the rotor with respect to the housing.

Abstract: A method of operating a universal flash storage (UFS) device communicating with a UFS host via a link is provided. The method determines in the UFS device whether a warm reset of the link is necessary while the UFS device is communicating with the UFS host via the link. Upon determining that the warm reset of the link is necessary, the UFS device initiates the warm reset of the link.

Abstract: A method for operating a system including a memory device and a host is provided. The method includes requesting, by the host, the memory device to transmit a context ID list including context IDs, assigning, by the host, a context ID among the context IDs to an application based on the context ID list received from the memory device, and transmitting, by the host, the context ID assigned to the application to the memory device when the host transmits a file corresponding to the application to the memory device or receives the file from the memory device.

Abstract: Narrow-channel effect free DRAM cell transistor structure for submicron isolation pitch DRAMs having lowed-doped substrate and active width-independent threshold voltage by employing conductive shield in the shallow trench isolation(STI). The resulting cell transistor structure is highly immune to parasitic E-field penetration from the gate and neighbouring storage node junctions via STI and will be very appropriate for Gbit scale DRAM technology. The conductive shield is biased with the negative voltage in order to minimize the sidewall depletion in the substrate.