Abstract: A pixel includes: a light emitting element; a first transistor including a gate electrode electrically connected to a first node, a second node to which a first power voltage for driving the light emitting element is to be applied, and a third node electrically connected to the light emitting element; and a bias control transistor configured to be controlled in operating timing thereof by a bias control signal, and configured to switch electrical connection between the second node and a bias power line for transmitting a bias voltage. In one frame period, a voltage level of the bias voltage to be applied to the second node sequentially increases.

Abstract: A display device includes a substrate, a first conductive layer on the substrate, the first conductive layer including a data signal line, a first insulating layer on the first conductive layer, a semiconductor layer on the first insulating layer, the semiconductor layer including a first semiconductor pattern, a second insulating layer on the semiconductor layer, and a second conductive layer on the second insulating layer, the second conductive layer including a gate electrode disposed to overlap the first semiconductor pattern, a transistor first electrode disposed to overlap a part of the first semiconductor pattern, wherein the transistor first electrode is electrically connected to the data signal line through a contact hole that penetrates the first and second insulating layers, and a transistor second electrode disposed to overlap another part of the first semiconductor pattern.

Abstract: A pixel includes: a first transistor including a gate electrode electrically connected to a first node, a second node to which a first power voltage for driving the light emitting element is applied, and a third node electrically connected to the light emitting element; a first emission control transistor having an on-off timing controlled by a first emission control signal; and a second emission control transistor having an on-off timing controlled by a second emission control signal. A time interval exists between a time at which the first emission control signal having a turn-on level is input such that a voltage of the second node is dropped from a bias voltage having a voltage level higher than a voltage level of the first power voltage and a time at which the second emission control signal having a turn-on level is input.

Abstract: A gene amplification chip includes a chamber layer, a cover layer, a bottom layer, an inlet, and an outlet. The chamber layer has a first passage and through holes which are formed on one side of the first passage. The cover layer is disposed on one side of the chamber layer and has a cover channel formed to communicate with the first passage and the through holes, wherein the cover channel, the first passage and the through holes allow passage of liquids in a divided manner. The bottom layer is disposed on another side of the chamber layer and has a bottom channel formed to communicate with the first passage and the through holes. The inlet is formed in the cover layer and communicates with the cover channel. The outlet communicates with any one of the cover channel and the bottom channel.

Abstract: A multilayer capacitor includes a body including a multilayer structure in which a plurality of dielectric layers are stacked in a first direction and a plurality of internal electrodes stacked with the dielectric layer interposed therebetween and external electrodes formed outside the body and connected to the internal electrodes. The body includes an active portion and a side margin portion covering the active portion and opposing each other in a second direction, and 1<A2/M1?1.5 and A2<A1 in which A1 is an average grain size of the dielectric layers in a central region of the active portion, A2 is an average grain size of the dielectric layers at an active boundary part of the active portion adjacent to the side margin portion, and M1 is an average grain size of the dielectric layers in a central region of the side margin portion.

Abstract: A pixel includes: a first transistor including a gate electrode electrically connected to a first node, a second node to which a first power voltage for driving the light emitting element is applied, and a third node electrically connected to the light emitting element; a first emission control transistor having an on-off timing controlled by a first emission control signal; and a second emission control transistor having an on-off timing controlled by a second emission control signal. A time interval exists between a time at which the first emission control signal having a turn-on level is input such that a voltage of the second node is dropped from a bias voltage having a voltage level higher than a voltage level of the first power voltage and a time at which the second emission control signal having a turn-on level is input.

Abstract: An optical sensor includes a substrate, a photoelectric element disposed on the substrate and that includes a first electrode, an intermediate layer disposed on the first electrode, and a second electrode disposed on the intermediate layer, a barrier layer disposed on the second electrode, an insulating layer that covers the photoelectric element and the barrier layer, and a bias electrode disposed on the insulating layer and electrically connected to the second electrode. The barrier layer is spaced apart from the first electrode.

Abstract: A method and an electronic device for translating a speech signal between a first language and a second language with minimized translation delay by translating fewer than all words of the speech signal according to a level of understanding of the second language by a user that receives the translation.

Abstract: A multilayer electronic component includes a body including a plurality of dielectric layers, side margin portions disposed on the body, and external electrodes disposed on the body. The reliability of the multilayer electronic component is improved by controlling the contents of Si for each position of the dielectric layer and the side margin portion.

Abstract: According to some embodiments of the present disclosure, a semiconductor device includes a first power rail configured to provide a first voltage and extending in a first direction, a substrate comprising a first well having a first conductivity type and a second well having a second conductivity type, a first well tap having the first conductivity type, on the first well; a first source/drain region having the second conductivity type, on the first well; a first source/drain contact extending in a second direction and electrically connected to the first power rail, on the first source/drain region, a first connection wiring electrically connected to the first source/drain contact and extending in the first direction, and a first well contact electrically connected to the first connection wiring, on the first well tap.

Abstract: An integrated circuit includes first power supply lines which extend in a first direction and are spaced apart from each other in a second direction different from the first direction. A second power supply line extends in the first direction and is placed between the first power supply lines adjacent to each other in the second direction. A decoupling filler cell is placed between the first power supply lines adjacent to each other in the second direction. The decoupling filler cell includes a decoupling capacitor region formed by a gate electrode and a decap transistor including a first source/drain region of a first conductive type. The gate electrode is connected to the second power supply line, the first source/drain region is connected to the first power supply lines, and the second power supply line passes through the decoupling capacitor region.

Abstract: A safety barrier includes: a body installed on a road; a steel plate portion placed between the body and the road; and an anchor portion passing through the steel plate portion and having an upper part buried in the body and a lower part buried in the road, wherein a first space in which a middle part of the anchor portion other than the upper part and the lower part is placed, is formed between the body and the road, and when an impact is applied to the body, the body is moved while accompanying bending deformation of the middle part in the first space so that the impact is absorbed, and after bending deformation of the middle part occurs, the steel plate portion breaks the anchor portion to implement further movement of the body caused by the impact so that the impact is dispersed.

Abstract: A scan flip-flop includes an input unit and a flip-flop. The input unit is configured to select one signal from among a data input signal and a scan input signal to supply the selected one signal as an internal signal according to an operation mode. The flip-flop is configured to latch the internal signal according to a clock signal. The flip-flop includes a cross coupled structure that includes first and second tri-state inverters which share a first output node and face each other.

Abstract: The present disclosure relates to a peritoneal cavity-bladder connecting catheter for ascites drainage. The peritoneal cavity-bladder connecting catheter for ascites drainage includes a peritoneal cavity position part positioned on the side of a peritoneal cavity by passing through a bladder wall located between the peritoneal cavity and a bladder, the peritoneal cavity position part having inlets through which ascites flow into an inner space and being formed as a film that surrounds the inner space, and a bladder position part integrally formed with the peritoneal cavity position part and positioned on the side of the bladder located on the side of the bladder wall opposite to the peritoneal cavity, the bladder position part having outlets through ascites flowed into the peritoneal cavity position part are discharged to outside, and being configured to form a closed inner space together with the peritoneal cavity position part.

Abstract: A scan flip-flop includes an input unit and a flip-flop. The input unit is configured to select one signal from among a data input signal and a scan input signal to supply the selected one signal as an internal signal according to an operation mode. The flip-flop is configured to latch the internal signal according to a clock signal. The flip-flop includes a cross coupled structure that includes first and second tri-state inverters which share a first output node and face each other.

Abstract: A safety barrier includes: a body installed on a road; a steel plate portion placed between the body and the road; and an anchor portion passing through the steel plate portion and having an upper part buried in the body and a lower part buried in the road, wherein a first space in which a middle part of the anchor portion other than the upper part and the lower part is placed, is formed between the body and the road, and when an impact is applied to the body, the body is moved while accompanying bending deformation of the middle part in the first space so that the impact is absorbed, and after bending deformation of the middle part occurs, the steel plate portion breaks the anchor portion to implement further movement of the body caused by the impact so that the impact is dispersed.

Abstract: A scan flip-flop includes an input unit and a flip-flop. The input unit is configured to select one signal from among a data input signal and a scan input signal to supply the selected one signal as an internal signal according to an operation mode. The flip-flop is configured to latch the internal signal according to a clock signal. The flip-flop includes a cross coupled structure that includes first and second tri-state inverters which share a first output node and face each other.

Abstract: A scan flip-flop includes an input unit and a flip-flop. The input unit is configured to select one signal from among a data input signal and a scan input signal to supply the selected one signal as an internal signal according to an operation mode. The flip-flop is configured to latch the internal signal according to a clock signal. The flip-flop includes a cross coupled structure that includes first and second tri-state inverters which share a first output node and face each other.

Abstract: A scan flip-flop includes an input unit and a flip-flop. The input unit is configured to select one signal from among a data input signal and a scan input signal to supply the selected one signal as an internal signal according to an operation mode. The flip-flop os configured to latch the internal signal according to a clock signal. The flip-flop includes a cross coupled structure that includes first and second tri-state inverters which share a first output node and face each other.

Abstract: A bidirectional delay circuit includes an input driving circuit and a delay switch circuit. The input driving circuit is connected between an input node and an intermediate node, and the input driving circuit amplifies an input signal received through the input node to generate an intermediate signal through the intermediate node. The delay switch circuit is connected between the intermediate node and a delay node, and the delay switch circuit delays both of rising edges and falling edges of the intermediate signal in response to a gate signal to generate a delay signal through the delay node. The gate signal may transition in response to the input signal.