Patents by Inventor Jae Han Chung

Jae Han Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150084178
    Abstract: An integrated circuit packaging system, and method of manufacture therefor, includes: a substrate; a mold cap formed on the substrate; fiducial mark inscribed in the mold cap; a thermal interface material applied over the substrate and referenced by the fiducial mark; and a heat spreader, mounted on the thermal interface material, precisely positioned by a position notch aligned relative to the fiducial mark.
    Type: Application
    Filed: September 25, 2013
    Publication date: March 26, 2015
    Inventors: Oh Han Kim, SeIl Jung, HeeSoo Lee, Jae Han Chung, YoungChul Kim
  • Patent number: 8710634
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate having a substrate-interconnect; mounting an integrated circuit above and to the substrate; mounting an internal interconnect to the substrate-interconnect; mounting a structure having an integral-interposer-structure over the substrate and over the integrated circuit with the integral-interposer-structure connected to the internal interconnect; and encapsulating the internal interconnect and the integrated circuit with an encapsulation.
    Type: Grant
    Filed: March 25, 2009
    Date of Patent: April 29, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: HeeJo Chi, Jae Han Chung, Junwoo Myung, Yeonglm Park, HyungMin Lee
  • Publication number: 20130322023
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching an integrated circuit to the substrate; molding an encapsulation directly on the integrated circuit and the substrate; forming a trench in the encapsulation having a trench bottom surface and surrounding the integrated circuit; and mounting a heatsink having a heatsink rim over the integrated circuit with the heatsink rim within the trench and the heatsink electrically isolated from the substrate.
    Type: Application
    Filed: June 5, 2012
    Publication date: December 5, 2013
    Inventors: Gwangjin Kim, JoungIn Yang, DokOk Yu, Hoon Jung, Jae Han Chung
  • Publication number: 20120223435
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a base package having a base integrated circuit over a base substrate; stacking a mountable device over the base package with a flow channel between the mountable device and the base package; and forming an external lead having a lead platform and a lead leg, the lead platform extending from the mountable device and the lead leg parallel to the base package.
    Type: Application
    Filed: March 1, 2011
    Publication date: September 6, 2012
    Inventors: A Leam Choi, Jae Han Chung, DeokKyung Yang
  • Patent number: 8247894
    Abstract: An integrated circuit package system includes: providing a stackable integrated circuit package system having a base encapsulation and a recess therein; stacking a top integrated circuit package system, having a top encapsulation with a protruding portion, with the stackable integrated circuit package system with the protruding portion aligned and matched within the recess; and connecting the top integrated circuit package system and the stackable integrated circuit package system.
    Type: Grant
    Filed: March 24, 2008
    Date of Patent: August 21, 2012
    Assignee: STATS ChipPAC Ltd.
    Inventors: In Sang Yoon, HanGil Shin, Jae Han Chung, DeokKyung Yang
  • Patent number: 8093100
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a through silicon via die having an interconnect through a silicon substrate; depositing a re-distribution layer on the through silicon via die and connected to the interconnects; mounting a structure over the through silicon via die; connecting the structure to the interconnect of the through silicon via die with a direct interconnect; and encapsulating the through silicon via die and partially encapsulating the structure with an encapsulation.
    Type: Grant
    Filed: November 19, 2010
    Date of Patent: January 10, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: A Leam Choi, Jae Han Chung, DeokKyung Yang, HyungSang Park
  • Patent number: 8067831
    Abstract: An integrated circuit package system is provided including forming a first substrate, mounting a first integrated circuit to the first substrate, and forming first planar interconnects in contact with the first integrated circuit and electrically connecting the first integrated circuit to the first substrate.
    Type: Grant
    Filed: September 16, 2005
    Date of Patent: November 29, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Hyeog Chan Kwon, Tae Sung Jeong, Jae Han Chung, Taeg Ki Lim, Jong Wook Ju
  • Publication number: 20110062591
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a through silicon via die having an interconnect through a silicon substrate; depositing a re-distribution layer on the through silicon via die and connected to the interconnects; mounting a structure over the through silicon via die; connecting the structure to the interconnect of the through silicon via die with a direct interconnect; and encapsulating the through silicon via die and partially encapsulating the structure with an encapsulation.
    Type: Application
    Filed: November 19, 2010
    Publication date: March 17, 2011
    Inventors: A Leam Choi, Jae Han Chung, DeokKyung Yang, HyungSang Park
  • Patent number: 7875967
    Abstract: An integrated circuit package system including: providing a substrate; mounting an integrated circuit above the substrate; mounting an inner stacking module, having an inner stacking module encapsulation and a molded integral step molded in the inner stacking module encapsulation, above the integrated circuit; and encapsulating the inner stacking module, and the integrated circuit with an encapsulation.
    Type: Grant
    Filed: March 10, 2008
    Date of Patent: January 25, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: DeokKyung Yang, In Sang Yoon, Jae Han Chung
  • Patent number: 7859099
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a through silicon via die having an interconnect through a silicon substrate; depositing a re-distribution layer on the through silicon via die and connected to the interconnects; mounting a structure over the through silicon via die; connecting the structure to the interconnect of the through silicon via die with a direct interconnect; and encapsulating the through silicon via die and partially encapsulating the structure with an encapsulation.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: December 28, 2010
    Assignee: Stats Chippac Ltd.
    Inventors: A Leam Choi, Jae Han Chung, DeokKyung Yang, HyungSang Park
  • Publication number: 20100244222
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate having a substrate-interconnect; mounting an internal-interconnect to the substrate-interconnect; mounting a structure having an integral-interposer-structure over the substrate with the integral-interposer-structure connected to the internal-interconnect; mounting an integrated circuit to the substrate and under the integral-interposer-structure; and encapsulating the internal-interconnect and the integrated circuit with an encapsulation.
    Type: Application
    Filed: March 25, 2009
    Publication date: September 30, 2010
    Inventors: HeeJo Chi, Jae Han Chung, Junwoo Myung, YeongIm Park, HyungMin Lee
  • Publication number: 20100148354
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a through silicon via die having an interconnect through a silicon substrate; depositing a re-distribution layer on the through silicon via die and connected to the interconnects; mounting a structure over the through silicon via die; connecting the structure to the interconnect of the through silicon via die with a direct interconnect; and encapsulating the through silicon via die and partially encapsulating the structure with an encapsulation.
    Type: Application
    Filed: December 11, 2008
    Publication date: June 17, 2010
    Inventors: A Leam Choi, Jae Han Chung, DeokKyung Yang, HyungSang Park
  • Patent number: 7687920
    Abstract: An integrated circuit package-on-package system includes: providing a base substrate having a central opening; attaching a bottom die below the base substrate partially covering the central opening, the bottom die connected through the central opening to a top surface of the base substrate; attaching a top die above the base substrate partially covering the central opening; attaching external conductive interconnections to a base bottom surface of the base substrate; and molding an encapsulant leaving the external conductive interconnections partially exposed.
    Type: Grant
    Filed: April 11, 2008
    Date of Patent: March 30, 2010
    Assignee: Stats Chippac Ltd.
    Inventors: DeokKyung Yang, Jae Han Chung, Hyun Joung Kim
  • Publication number: 20090256267
    Abstract: An integrated circuit package-on-package system includes: providing a base substrate having a central opening; attaching a bottom die below the base substrate partially covering the central opening, the bottom die connected through the central opening to a top surface of the base substrate; attaching a top die above the base substrate partially covering the central opening; attaching external conductive interconnections to a base bottom surface of the base substrate; and molding an encapsulant leaving the external conductive interconnections partially exposed.
    Type: Application
    Filed: April 11, 2008
    Publication date: October 15, 2009
    Inventors: DeokKyung Yang, Jae Han Chung, Hyun Joung Kim
  • Publication number: 20090236720
    Abstract: An integrated circuit package system includes: providing a stackable integrated circuit package system having a base encapsulation and a recess therein; stacking a top integrated circuit package system, having a top encapsulation with a protruding portion, with the stackable integrated circuit package system with the protruding portion aligned and matched within the recess; and connecting the top integrated circuit package system and the stackable integrated circuit package system.
    Type: Application
    Filed: March 24, 2008
    Publication date: September 24, 2009
    Inventors: In Sang Yoon, HanGil Shin, Jae Han Chung, DeokKyung Yang
  • Publication number: 20090224390
    Abstract: An integrated circuit package system including: providing a substrate; mounting an integrated circuit above the substrate; mounting an inner stacking module, having an inner stacking module encapsulation and a molded integral step molded in the inner stacking module encapsulation, above the integrated circuit; and encapsulating the inner stacking module, and the integrated circuit with an encapsulation.
    Type: Application
    Filed: March 10, 2008
    Publication date: September 10, 2009
    Inventors: DeokKyung Yang, In Sang Yoon, Jae Han Chung
  • Publication number: 20090127715
    Abstract: A mountable integrated circuit package system includes: mounting a first integrated circuit device over a carrier; mounting a second integrated circuit device over the first integrated circuit device includes: attaching the second integrated circuit device to a first substrate side of a substrate, and connecting a first electrical interconnect between the second integrated circuit device and a second substrate side of the substrate through an opening in the substrate. The mountable integrated circuit package system further including: forming a package encapsulation over the first integrated circuit device and the carrier with the substrate partially exposed.
    Type: Application
    Filed: November 15, 2007
    Publication date: May 21, 2009
    Inventors: HanGil Shin, In Sang Yoon, Jae Han Chung
  • Publication number: 20080315406
    Abstract: An integrated circuit package system includes a base substrate having a base substrate cavity, attaching a junction integrated circuit package over the base substrate with a portion of the junction integrated circuit package in the base substrate cavity, and attaching a base integrated circuit over the junction integrated circuit package and the base substrate.
    Type: Application
    Filed: June 25, 2007
    Publication date: December 25, 2008
    Inventors: Jae Han Chung, HeeJo Chi, HanGil Shin, SunMi Kim
  • Patent number: 7445962
    Abstract: A stacked integrated circuits package system is provided providing a first substrate, mounting a first integrated circuit on a second substrate, attaching the first integrated circuit, by a side opposite the second substrate, to the first substrate, mounting a second integrated circuit to the second substrate, connecting the second integrated circuit to the first substrate, and attaching a heat spreader to the second integrated circuit and the first substrate.
    Type: Grant
    Filed: December 16, 2005
    Date of Patent: November 4, 2008
    Assignee: Stats Chippac Ltd.
    Inventors: Bongsuk Choi, Jae Han Chung, Keon Teak Kang
  • Publication number: 20070063331
    Abstract: An integrated circuit package system is provided including forming a first substrate, mounting a first integrated circuit to the first substrate, and forming first planar interconnects in contact with the first integrated circuit and electrically connecting the first integrated circuit to the first substrate.
    Type: Application
    Filed: September 16, 2005
    Publication date: March 22, 2007
    Applicant: STATS CHIPPAC LTD.
    Inventors: Hyeog Chan Kwon, Tae Sung Jeong, Jae Han Chung, Taeg Ki Lim, Jong Wook Ju