Abstract: The present invention relates to a semiconductor device having a capacitor and a method for fabricating the same. A semiconductor device may comprise: a lower electrode; a supporter supporting an outer wall of the lower electrode; a dielectric layer formed over the lower electrode and the supporter; an upper electrode formed on the dielectric layer; and a dielectric booster layer disposed between the lower electrode and the dielectric layer, and selectively formed on a surface of the lower electrode.

Abstract: The present invention relates to a semiconductor device having a capacitor and a method for fabricating the same. A semiconductor device may comprise: a lower electrode; a supporter supporting an outer wall of the lower electrode; a dielectric layer formed over the lower electrode and the supporter; an upper electrode formed on the dielectric layer; and a dielectric booster layer disposed between the lower electrode and the dielectric layer, and selectively formed on a surface of the lower electrode.

Abstract: A semiconductor device includes a lower electrode; a supporter supporting an outer wall of the lower electrode; a dielectric layer formed on the lower electrode and the supporter; an upper electrode on the dielectric layer; a first interfacial layer disposed between the lower electrode and the dielectric layer and selectively formed on a surface of the lower electrode among the lower electrode and the supporter; and a second interfacial layer disposed between the dielectric layer and the upper electrode, wherein the first interfacial layer is a stack of a metal oxide contacting the lower electrode and a metal nitride contacting the dielectric layer.

Abstract: A semiconductor device includes a lower electrode; a supporter supporting an outer wall of the lower electrode; a dielectric layer formed on the lower electrode and the supporter; an upper electrode on the dielectric layer; a first interfacial layer disposed between the lower electrode and the dielectric layer and selectively formed on a surface of the lower electrode among the lower electrode and the supporter; and a second interfacial layer disposed between the dielectric layer and the upper electrode, wherein the first interfacial layer is a stack of a metal oxide contacting the lower electrode and a metal nitride contacting the dielectric layer.

Abstract: A semiconductor device includes a lower electrode; a supporter supporting an outer wall of the lower electrode; a dielectric layer formed on the lower electrode and the supporter; an upper electrode on the dielectric layer; a first interfacial layer disposed between the lower electrode and the dielectric layer and selectively formed on a surface of the lower electrode among the lower electrode and the supporter; and a second interfacial layer disposed between the dielectric layer and the upper electrode, wherein the first interfacial layer is a stack of a metal oxide contacting the lower electrode and a metal nitride contacting the dielectric layer.

Abstract: A semiconductor device includes a lower electrode; a supporter supporting an outer wall of the lower electrode; a dielectric layer formed on the lower electrode and the supporter; an upper electrode on the dielectric layer; a first interfacial layer disposed between the lower electrode and the dielectric layer and selectively formed on a surface of the lower electrode among the lower electrode and the supporter; and a second interfacial layer disposed between the dielectric layer and the upper electrode, wherein the first interfacial layer is a stack of a metal oxide contacting the lower electrode and a metal nitride contacting the dielectric layer.

Abstract: The present invention relates to a semiconductor device having a capacitor and a method for fabricating the same. A semiconductor device may comprise: a lower electrode; a supporter supporting an outer wall of the lower electrode; a dielectric layer formed over the lower electrode and the supporter; an upper electrode formed on the dielectric layer; and a dielectric booster layer disposed between the lower electrode and the dielectric layer, and selectively formed on a surface of the lower electrode.

Abstract: An ultrasound diagnostic apparatus to improve picture quality of images by automatically adjusting image parameters, and a control method thereof are provided. The ultrasound diagnostic apparatus includes an image signal processor to perform envelope detection processing on ultrasound image data, and an image parameter processor to calculate a Time Gain Compensation (TGC) parameter from the envelope detection processed ultrasound image data, adjust the envelope detection processed ultrasound image data based on the TGC parameter, and calculate a Dynamic Range (DR) parameter from the envelope detection processed ultrasound image data adjusted based on the TGC parameter to apply the DR parameter to the envelope detection processed ultrasound image data.

Abstract: An ultrasound diagnostic apparatus to improve picture quality of images by automatically adjusting image parameters, and a control method thereof are provided. The ultrasound diagnostic apparatus includes an image signal processor to perform envelope detection processing on ultrasound image data, and an image parameter processor to calculate a Time Gain Compensation (TGC) parameter from the envelope detection processed ultrasound image data, adjust the envelope detection processed ultrasound image data based on the TGC parameter, and calculate a Dynamic Range (DR) parameter from the envelope detection processed ultrasound image data adjusted based on the TGC parameter to apply the DR parameter to the envelope detection processed ultrasound image data.

Abstract: A beamforming apparatus is provided for improving beamforming accuracy by employing fractional delay filters in an interpolation process and reducing hardware complexity by using post-filtering technique. The beamforming apparatus of the present invention includes a post-filtering means implemented with fractional delay filters that combines block data, on the respective channels, supposed to be fractionally delayed and obtains a delay value of fractional part from the combined data. The post-filtering means collects the block data of the channels assigned identical coefficients and performs a filtering process simultaneously.

Abstract: Disclosed herein is a harmonic quadrature demodulation apparatus and method. The harmonic quadrature demodulation apparatus includes an input terminal for externally receiving an input focused signal, a harmonic phase estimation unit for estimating a second-order harmonic phase component from the input focused signal. The second-order harmonic detection unit includes an in-phase component extractor, a quadrature component extratctor, a Hilbert transformer, an adder and a low pass filter. The in-phase component extractor extracts an in-phase component of the input focused signal. The quadrature component extractor extracts a quadrature component of the input focused signal.

Abstract: Disclosed herein is an apparatus and method for extracting a second harmonic signal. The apparatus removes a fundamental frequency signal from a reception signal and then extracting the second harmonic signal. A transmitter generates a transmission signal by modulating a reference signal, and then transmits the transmission signal. A receiver extracts the second harmonic components of the reception signal by demodulating the reception signal received after the transmission signal is reflected by an external media. The transmitter includes a reference signal input unit, a first phase modulation unit, a second phase modulation unit, and a transmission signal output unit. The receiver includes a reception signal input unit, a first output signal generation unit, a second output signal generation unit, and a signal output unit.

Abstract: Disclosed herein is a harmonic quadrature demodulation apparatus and method. The harmonic quadrature demodulation apparatus includes an input terminal for externally receiving an input focused signal, a harmonic phase estimation unit for estimating a second-order harmonic phase component from the input focused signal, and a harmonic detection unit for detecting a second-order harmonic component from the input focused signal. The second-order harmonic detection unit includes an in-phase component extractor, a quadrature component extractor, a Hilbert transformer, an adder and a low pass filter. The in-phase component extractor extracts an in-phase component of the input focused signal. The quadrature component extractor extracts a quadrature component of the input focused signal. The Hilbert transformer Hilbert-transforms a signal transmitted from the quadrature component extractor.

Abstract: A beamforming apparatus is provided for improving beamforming accuracy by employing fractional delay filters in an interpolation process and reducing hardware complexity by using post-filtering technique. The beamforming apparatus of the present invention includes a post-filtering means implemented with fractional delay filters that combines block data, on the respective channels, supposed to be fractionally delayed and obtains a delay value of fractional part from the combined data. The post-filtering means collects the block data of the channels assigned identical coefficients and performs a filtering process simultaneously.