Patents by Inventor Jae Ho Joung
Jae Ho Joung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10733354Abstract: Disclosed are embodiments of a system, method and computer program product for wafer-level design including chip and frame design. The embodiments employ three-dimensional (3D) emulation to preliminarily verify in-kerf optical macros included in a frame design layout. Specifically, 3D images of a given in-kerf optical macro at different process steps are generated by a 3D emulator and a determination is made as to whether or not that macro will be formed as predicted. If not, the plan for the macro is altered using an iterative design process. Once the in-kerf optical macros within the frame design layout have been preliminarily verified, wafer-level design layout verification, including chip and frame design layout verification, is performed. Once the wafer-level design layout has been verified, wafer-level design layout validation, including chip and frame design layout validation, is performed. Optionally, an emulation library can store results of 3D emulation processes for future use.Type: GrantFiled: December 19, 2018Date of Patent: August 4, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Hojin Kim, Dongyue Yang, Dong-Ick Lee, Yue Zhou, Jae Ho Joung, Gregory Costrini, El Mehdi Bazizi, Dongsuk Park
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Publication number: 20200201955Abstract: Disclosed are embodiments of a system, method and computer program product for wafer-level design including chip and frame design. The embodiments employ three-dimensional (3D) emulation to preliminarily verify in-kerf optical macros included in a frame design layout. Specifically, 3D images of a given in-kerf optical macro at different process steps are generated by a 3D emulator and a determination is made as to whether or not that macro will be formed as predicted. If not, the plan for the macro is altered using an iterative design process. Once the in-kerf optical macros within the frame design layout have been preliminarily verified, wafer-level design layout verification, including chip and frame design layout verification, is performed. Once the wafer-level design layout has been verified, wafer-level design layout validation, including chip and frame design layout validation, is performed. Optionally, an emulation library can store results of 3D emulation processes for future use.Type: ApplicationFiled: December 19, 2018Publication date: June 25, 2020Inventors: Hojin Kim, Dongyue Yang, Dong-Ick Lee, Yue Zhou, Jae Ho Joung, Gregory Costrini, El Mehdi Bazizi, Dongsuk Park
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Patent number: 9871096Abstract: A capacitor includes a bottom electrode and a top electrode positioned above the bottom electrode. The top electrode and the bottom electrode are conductively coupled to one another. A middle electrode is positioned between the bottom electrode and the top electrode. A lower dielectric layer is positioned between the bottom electrode and the middle electrode. An upper dielectric layer is positioned between the middle electrode and the top electrode. A first contact is conductively coupled to the top electrode. A second contact is conductively coupled to the middle electrode.Type: GrantFiled: March 15, 2017Date of Patent: January 16, 2018Assignee: GLOBALFOUNDRIES Inc.Inventors: Ki Young Lee, Woong Lae Cho, Jae Ho Joung
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Publication number: 20170250243Abstract: A capacitor includes a bottom electrode and a top electrode positioned above the bottom electrode. The top electrode and the bottom electrode are conductively coupled to one another. A middle electrode is positioned between the bottom electrode and the top electrode. A lower dielectric layer is positioned between the bottom electrode and the middle electrode. An upper dielectric layer is positioned between the middle electrode and the top electrode. A first contact is conductively coupled to the top electrode. A second contact is conductively coupled to the middle electrode.Type: ApplicationFiled: March 15, 2017Publication date: August 31, 2017Inventors: Ki Young LEE, Woong Lae CHO, Jae Ho JOUNG
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Patent number: 9679959Abstract: Capacitor and contact structures are provided, as well as methods for forming the capacitor and contact structures. The methods include, for instance, providing a layer of conductive material above a conductive structure and above a lower electrode of a capacitor; etching the layer of conductive material to define a conductive material hard mask and an upper electrode of the capacitor, the conductive material hard mask being disposed at least partially above the conductive structure; and forming a first conductive contact structure and a second conductive contact structure, the first conductive contact structure extending through an opening in the conductive material hard mask and conductively contacting the conductive structure, and the second conductive contact structure conductively contacting one of the lower electrode of the capacitor, or the upper electrode of the capacitor.Type: GrantFiled: August 27, 2015Date of Patent: June 13, 2017Assignee: GLOBALFOUNDRIES Inc.Inventors: Ki Young Lee, Sanggil Bae, Jae Ho Joung
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Patent number: 9640608Abstract: A capacitor includes a bottom electrode and a top electrode positioned above the bottom electrode. The top electrode and the bottom electrode are conductively coupled to one another. A middle electrode is positioned between the bottom electrode and the top electrode. A lower dielectric layer is positioned between the bottom electrode and the middle electrode. An upper dielectric layer positioned between the middle electrode and the top electrode. A first contact is conductively coupled to the top electrode. A second contact is conductively coupled to the middle electrode.Type: GrantFiled: February 25, 2016Date of Patent: May 2, 2017Assignee: GLOBALFOUNDRIES Inc.Inventors: Ki Young Lee, Woong Lae Cho, Jae Ho Joung
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Publication number: 20150364540Abstract: Capacitor and contact structures are provided, as well as methods for forming the capacitor and contact structures. The methods include, for instance, providing a layer of conductive material above a conductive structure and above a lower electrode of a capacitor; etching the layer of conductive material to define a conductive material hard mask and an upper electrode of the capacitor, the conductive material hard mask being disposed at least partially above the conductive structure; and forming a first conductive contact structure and a second conductive contact structure, the first conductive contact structure extending through an opening in the conductive material hard mask and conductively contacting the conductive structure, and the second conductive contact structure conductively contacting one of the lower electrode of the capacitor, or the upper electrode of the capacitor.Type: ApplicationFiled: August 27, 2015Publication date: December 17, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Ki Young LEE, Sanggil BAE, Jae Ho JOUNG
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Patent number: 9178009Abstract: Methods of forming a capacitor and contact structures are provided. The methods include, for instance, providing a layer of conductive material above a conductive structure and above a lower electrode of a capacitor; etching the layer of conductive material to define a conductive material hard mask and an upper electrode of the capacitor, the conductive material hard mask being disposed at least partially above the conductive structure; and forming a first conductive contact structure and a second conductive contact structure, the first conductive contact structure extending through an opening in the conductive material hard mask and conductively contacting the conductive structure, and the second conductive contact structure conductively contacting one of the lower electrode of the capacitor, or the upper electrode of the capacitor.Type: GrantFiled: October 10, 2012Date of Patent: November 3, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: Ki Young Lee, Sanggil Bae, Jae Ho Joung
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Publication number: 20140098459Abstract: Capacitor and contact structures are provided, as well as methods for forming the capacitor and contact structures. The methods include, for instance, providing a layer of conductive material above a conductive structure and above a lower electrode of a capacitor; etching the layer of conductive material to define a conductive material hard mask and an upper electrode of the capacitor, the conductive material hard mask being disposed at least partially above the conductive structure; and forming a first conductive contact structure and a second conductive contact structure, the first conductive contact structure extending through an opening in the conductive material hard mask and conductively contacting the conductive structure, and the second conductive contact structure conductively contacting one of the lower electrode of the capacitor, or the upper electrode of the capacitor.Type: ApplicationFiled: October 10, 2012Publication date: April 10, 2014Applicant: GLOBALFOUNDRIES, INC.Inventors: Ki Young LEE, Sanggil BAE, Jae Ho JOUNG
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Patent number: 6597778Abstract: A method for setting a number plan and providing a service for an advanced intelligent network (AIN), includes the steps of searching a first trigger which corresponds to a detected AIN call, judging whether the first trigger is a second trigger for a subscriber group, searching subscriber group information of the first trigger when the first trigger is the second rigger and detecting an identification number of a PNP(Private Numbering Plan), searching a PNP corresponding to the identification number from a NTT(Number Translation Table) of the first trigger, and gathering an additional number based on number gathering information of the searched PNP and performing a number translation based on corresponding PNP, thereby setting a certain number plan by the subscriber group and providing a subscriber-based advanced intelligent network service.Type: GrantFiled: December 22, 1999Date of Patent: July 22, 2003Assignee: LG Information & Communication, Ltd.Inventors: Eun Soo Shin, Jae Ho Joung