Patents by Inventor Jae-Hun Jung

Jae-Hun Jung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11057770
    Abstract: The present invention relates to a method of dynamically changing a connection by a terminal in a wireless LAN. The method including determining a change of the connection to another wireless LAN and whether an access point (AP) of the first wireless LAN is the same as an AP of a second wireless LAN by comparing first AP identity determination information received from the first wireless LAN with second AP identity determination information received from the second wireless LAN and transmitting a message for requesting the connection to the second wireless LAN by using a temporary wireless LAN service profile generated on the basis of a wireless LAN service profile for the first wireless LAN, when the AP of the first wireless LAN is the same as the AP of the second wireless LAN.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: July 6, 2021
    Assignee: KT Corporation
    Inventors: Jae Hun Jung, Hae Seok Yang, Dong Hoo Lee, Han Jin Joh
  • Publication number: 20210074044
    Abstract: Provided are methods, servers, and recording mediums for creating a composite image. The method includes identifying a composition target object included in an input image, determining an insertion content associated with the identified composition target object, and synthesizing the insertion content with the region of the composition target object to create an output image.
    Type: Application
    Filed: September 1, 2020
    Publication date: March 11, 2021
    Applicant: LINE Plus Corporation
    Inventors: Jae-hun JUNG, Hae Seong CHOI
  • Patent number: 10938416
    Abstract: A memory device including a parity check circuit and a mask circuit may be provided. The parity check circuit may perform parity check on data sampled according to a data strobe signal, which does not include a post-amble. The mask circuit may generate a parity error signal based on results of the parity check, and output the parity error signal during a time period determined according to a burst length of the data.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: March 2, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hye-Seung Yu, Sukyong Kang, Wonjoo Yun, Hyunui Lee, Jae-Hun Jung
  • Publication number: 20200397644
    Abstract: A massage chair capable of massaging the front body region is proposed. In the massage chair, one end is rotatably coupled to the backrest part and the backrest part for supporting the user's back, and includes a front massage part for massaging the user's abdomen or chest. According to the present configuration, there is proposed a massage chair capable of performing massage even in a front body region of a person to be treated, such as a chest or an abdomen.
    Type: Application
    Filed: September 6, 2018
    Publication date: December 24, 2020
    Inventor: Jae Hun JUNG
  • Patent number: 10539217
    Abstract: A gear support device of an automatic transmission reduces vibration and noise that are generated in a planetary gear set when power is transmitted from a vehicle driving source. In particular, the gear support device includes a gear support which is disposed on an outer peripheral surface of a hub retainer coupled to a planetary gear set directly connected to an input shaft of a transmission. The gear support rotatably supports the hub retainer by contacting with the outer peripheral surface of the hub retainer at every predetermined interval in a circumferential direction of the hub retainer.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: January 21, 2020
    Assignees: HYUNDAI MOTOR COMPANY, KIA MOTORS CORPORATION
    Inventors: Jae Hun Jung, Jin Yong Kim, Yong Hoo Kim
  • Patent number: 10454317
    Abstract: A wireless power transmission device for wirelessly transmitting power to at least one wireless power reception device through a magnetic field, the wireless power transmission device including: a power transmission unit for generating a magnetic field, an impedance matching unit, and a control unit for controlling the impedance matching unit, the impedance matching unit including: a plurality of first circuits which include a capacitor or an inductor and are connected in series to the power transmission unit; a plurality of second circuits which include a capacitor or an inductor and are connected in parallel to the power transmission unit; a matching inductor which is connected in series to the second circuits; and a plurality of switches which are arranged in the first circuits and second circuits and open and close same.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: October 22, 2019
    Assignee: LS CABLE & SYSTEM LTD.
    Inventors: Sung-Han You, Jae-Sun Lee, Young-Sun Kim, Jae-Hun Jung, Un-Kyu Park
  • Patent number: 10436844
    Abstract: A synthetic test circuit for testing a submodule performance in a power compensator includes a submodule test unit which is an object of testing the submodule performance, a current source and a controller. The current source is connected to the submodule test unit to supply a voltage to the submodule test unit such that a charging voltage having a capacity set in the submodule test unit is stored in order to operate the submodule test unit. The controller is configured to perform control to perform a submodule performance test of the submodule test unit using the stored charging voltage.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: October 8, 2019
    Assignee: LSIS CO., LTD.
    Inventors: Yong Ho Chung, Seung Taek Baek, Young Woo Kim, Jin Hee Lee, Eui Cheol Nho, Jae Hun Jung
  • Patent number: 10367490
    Abstract: An electronic circuit may include a driver, a delay circuit, a strength control circuit, and an adder circuit. The driver may generate a second signal based on a first signal. The delay circuit may delay the first signal by as much as a reference time, to generate a third signal. The strength control circuit may adjust an amplitude of the third signal to generate a fourth signal. The adder circuit may add the second signal and the fourth signal to generate a fifth signal. In a first time interval determined based on the reference time, an amplitude of the fifth signal may be greater than an amplitude of the second signal. In a second time interval except for the first time interval, the amplitude of the fifth signal may be smaller than the amplitude of the second signal. In the second time interval, the amplitude of the fifth signal may be smaller than an amplitude of the first signal.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: July 30, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wangsoo Kim, Hangi Jung, Kiduk Park, Yoo-Chang Sung, Jae-Hun Jung, Cheongryong Cho, Hun-Dae Choi
  • Patent number: 10354704
    Abstract: A semiconductor memory device divides a clock signal to generate a first clock signal and a second clock signal, outputs a chip selection signal as a first chip selection signal in response to the first clock signal, outputs the buffered chip selection signal as a second chip selection signal in response to the second clock signal, outputs the first chip selection signal as a third chip selection signal in response to the second clock signal, outputs a buffered command and address as a first command and address in response to the first clock signal, outputs the buffered command and address as a second command and address in response to the second clock signal, outputs the first chip selection signal as a first selection signal in response to the first clock signal, and outputs the third chip selection signal as a second selection signal in response to the second clock signal.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: July 16, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae Hun Jung, Hun Dae Choi
  • Publication number: 20190180803
    Abstract: A semiconductor memory device divides a clock signal to generate a first clock signal and a second clock signal, outputs a chip selection signal as a first chip selection signal in response to the first clock signal, outputs the buffered chip selection signal as a second chip selection signal in response to the second clock signal, outputs the first chip selection signal as a third chip selection signal in response to the second clock signal, outputs a buffered command and address as a first command and address in response to the first clock signal, outputs the buffered command and address as a second command and address in response to the second clock signal, outputs the first chip selection signal as a first selection signal in response to the first clock signal, and outputs the third chip selection signal as a second selection signal in response to the second clock signal.
    Type: Application
    Filed: May 24, 2018
    Publication date: June 13, 2019
    Inventors: JAE HUN JUNG, HUN DAE CHOI
  • Publication number: 20190182736
    Abstract: The present invention relates to a method of dynamically changing a connection by a terminal in a wireless LAN. The method including determining a change of the connection to another wireless LAN and whether an access point (AP) of the first wireless LAN is the same as an AP of a second wireless LAN by comparing first AP identity determination information received from the first wireless LAN with second AP identity determination information received from the second wireless LAN and transmitting a message for requesting the connection to the second wireless LAN by using a temporary wireless LAN service profile generated on the basis of a wireless LAN service profile for the first wireless LAN, when the AP of the first wireless LAN is the same as the AP of the second wireless LAN.
    Type: Application
    Filed: May 26, 2017
    Publication date: June 13, 2019
    Applicant: KT Corporation
    Inventors: Jae Hun JUNG, Hae Seok YANG, Dong Hoo LEE, Han Jin JOH
  • Publication number: 20190165808
    Abstract: A memory device including a parity check circuit and a mask circuit may be provided. The parity check circuit may perform parity check on data sampled according to a data strobe signal, which does not include a post-amble. The mask circuit may generate a parity error signal based on results of the parity check, and output the parity error signal during a time period determined according to a burst length of the data.
    Type: Application
    Filed: January 30, 2019
    Publication date: May 30, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Hye-Seung YU, Sukyong KANG, Wonjoo YUN, Hyunui LEE, Jae-Hun JUNG
  • Publication number: 20190140628
    Abstract: An electronic circuit may include a driver, a delay circuit, a strength control circuit, and an adder circuit. The driver may generate a second signal based on a first signal. The delay circuit may delay the first signal by as much as a reference time, to generate a third signal. The strength control circuit may adjust an amplitude of the third signal to generate a fourth signal. The adder circuit may add the second signal and the fourth signal to generate a fifth signal. In a first time interval determined based on the reference time, an amplitude of the fifth signal may be greater than an amplitude of the second signal. In a second time interval except for the first time interval, the amplitude of the fifth signal may be smaller than the amplitude of the second signal. In the second time interval, the amplitude of the fifth signal may be smaller than an amplitude of the first signal.
    Type: Application
    Filed: July 3, 2018
    Publication date: May 9, 2019
    Inventors: WANGSOO KIM, Hangi Jung, Kiduk Park, Yoo-Chang Sung, Jae-Hun Jung, Cheongryong Cho, Hun-dae Choi
  • Patent number: 10243584
    Abstract: A memory device including a parity check circuit and a mask circuit may be provided. The parity check circuit may perform parity check on data sampled according to a data strobe signal, which does not include a post-amble. The mask circuit may generate a parity error signal based on results of the parity check, and output the parity error signal during a time period determined according to a burst length of the data.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: March 26, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hye-Seung Yu, Sukyong Kang, Wonjoo Yun, Hyunui Lee, Jae-Hun Jung
  • Publication number: 20180306304
    Abstract: A gear support device of an automatic transmission reduces vibration and noise that are generated in a planetary gear set when power is transmitted from a vehicle driving source. In particular, the gear support device includes a gear support which is disposed on an outer peripheral surface of a hub retainer coupled to a planetary gear set directly connected to an input shaft of a transmission. The gear support rotatably supports the hub retainer by contacting with the outer peripheral surface of the hub retainer at every predetermined interval in a circumferential direction of the hub retainer.
    Type: Application
    Filed: December 5, 2017
    Publication date: October 25, 2018
    Applicants: HYUNDAI MOTOR COMPANY, KIA MOTORS CORPORATION
    Inventors: Jae Hun JUNG, Jin Yong KIM, Yong Hoo KIM
  • Publication number: 20180136281
    Abstract: A synthetic test circuit for testing a submodule performance in a power compensator includes a submodule test unit which is an object of testing the submodule performance, a current source and a controller. The current source is connected to the submodule test unit to supply a voltage to the submodule test unit such that a charging voltage having a capacity set in the submodule test unit is stored in order to operate the submodule test unit. The controller is configured to perform control to perform a submodule performance test of the submodule test unit using the stored charging voltage.
    Type: Application
    Filed: August 22, 2017
    Publication date: May 17, 2018
    Applicants: LSIS CO., LTD., Pukyong National University Industry-University Cooperation Foundation
    Inventors: Yong Ho CHUNG, Seung Taek BAEK, Young Woo KIM, Jin Hee LEE, Eui Cheol NHO, Jae Hun JUNG
  • Patent number: 9966126
    Abstract: A delay circuit of a semiconductor memory device includes a delay chain, a first phase converter and a second phase converter. The delay chain is connected between an input terminal and an output terminal, includes 2N delay cells, and delays a first intermediate signal to generate a second intermediate signal. The first phase converter is connected to the input terminal, and provides the first intermediate signal to the delay chain, wherein the first intermediate signal is generated by inverting a phase of an input signal or by maintaining the phase of the input signal in response to a control signal. The second phase converter is connected to the output terminal, and generates an output signal by inverting a phase of the second intermediate signal or by maintaining the phase of the second intermediate signal in response to the control signal.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: May 8, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Oh Ahn, Sukyong Kang, Hye-Seung Yu, Jae-Hun Jung
  • Patent number: 9959935
    Abstract: An input-output circuit includes a reception circuit and a register circuit. The reception circuit operates in accordance with a normal write protocol commonly in a normal write mode and a test write mode. The reception circuit receives a plurality of input signals to generate a plurality of latch signals. The register circuit generates a plurality of test result signals based on the latch signals in the test write mode. The input-output circuit may perform the multiple-input shift register (MISR) function in accordance with the normal write path and the normal write protocol. The MISR function may be performed efficiently without consideration of additional timing adjustment for the test write operation because the MISR function is performed under the same timing condition as the normal write operation.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: May 1, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sukyong Kang, Won-Joo Yun, Hye-Seung Yu, Hyun-Ui Lee, Jae-Hun Jung
  • Patent number: 9869728
    Abstract: Embodiments of a synthetic test circuit for a valve performance test of high-voltage direct current (HVDC) are presented. In some embodiments, the synthetic test circuit comprises a resonance circuit configured to comprise a first test valve to test an operation of an inverter mode and a second test valve to test an operation of a rectifier mode. The synthetic test circuit may comprise a power supply (P/S) configured to provide the resonance circuit with an operating voltage. The synthetic test circuit may comprise a direct current/direct current (DC/DC) converter configured to bypass a DC offset current of the resonance circuit. The first test valve may be an inverter unit, which may have a positive DC current offset. Further, the second test valve may be a rectifier unit, which may have a negative DC current offset.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: January 16, 2018
    Assignee: LSIS CO., LTD
    Inventors: Seung Taek Baek, Eui Cheol Nho, Jae Hun Jung, Jin Hee Lee, Yong Ho Chung
  • Publication number: 20170372764
    Abstract: A delay circuit of a semiconductor memory device includes a delay chain, a first phase converter and a second phase converter. The delay chain is connected between an input terminal and an output terminal, includes 2N delay cells, and delays a first intermediate signal to generate a second intermediate signal. The first phase converter is connected to the input terminal, and provides the first intermediate signal to the delay chain, wherein the first intermediate signal is generated by inverting a phase of an input signal or by maintaining the phase of the input signal in response to a control signal. The second phase converter is connected to the output terminal, and generates an output signal by inverting a phase of the second intermediate signal or by maintaining the phase of the second intermediate signal in response to the control signal.
    Type: Application
    Filed: April 13, 2017
    Publication date: December 28, 2017
    Inventors: SUNG-OH AHN, Sukyong Kang, Hye-Seung Yu, Jae-Hun Jung