Abstract: Transistor structures with a dielectric trench plug below source and drain semiconductor material. Following frontside processing, a workpiece may be inverted and backside interconnect metallization fabricated. The dielectric trench plug can electrically insulate the backside interconnect metallization from source and drain semiconductor material. In some examples, a dielectric trench plug is formed during frontside processing, backfilling a trench in subfin semiconductor material prior to the deposition of source and drain semiconductor material. In other examples, a dielectric trench plug is formed during backside processing. When source or drain semiconductor material is exposed with a backside planarization polish, a recess may be etched in the exposed semiconductor material and the recess backfilled with the dielectric trench plug.

Abstract: Integrated circuit (IC) structures with lined source or drain regions, as well as related method and devices, are disclosed. In one aspect, an IC structure may include a channel region of a transistor, a first region proximate to a first end of the channel region, and a second region proximate to a second end of the channel region, wherein one of the first region and the second region is a source region of the transistor and another one of the first region and the second region is a drain region of the transistor, the first region includes a liner material and a fill material, the liner material is laterally between the fill material and the channel region, and a material composition of the liner material is different from a material composition of the fill material.

Abstract: An integrated circuit includes a source region and a drain region, and a body including semiconductor material extending between the source and drain regions. The body has first and second end portions, and a middle portion between the first and second end portions. The body includes an implant species, a concentration of the implant species in the middle portion of the body being 10% or more higher than a concentration of the implant species in the first and second end portions. The integrated circuit includes a gate structure on the middle portion of the body, a first gate spacer on the first end portion of the body, and a second gate spacer on the second end portion of the body. The implant species includes, for example, a non-dopant element having an atomic mass unit of 80 or less, or a halide, e.g., one of fluorine, chlorine, argon, or boron.

Abstract: An integrated circuit structure comprises a fin extending from a substrate, the fin comprising source and drain regions, and a channel region between the source and drain regions. A multilayer high-k gate stack comprising a plurality of materials extends conformally over the fin over the channel region. A gate electrode is over and on a topmost material in the multilayer high-k gate stack. Fluorine is implanted in the substrate beneath the multilayer high-k gate stack or in the plurality of materials comprising the multilayer high-k gate stack.

Abstract: A two-terminal biristor in which a polysilicon emitter layer is inserted and a method of manufacturing the same are provided. The method of manufacturing the two-terminal biristor according to an embodiment of the present disclosure includes forming a first semiconductor layer of a first type on a substrate, forming a second semiconductor layer of a second type on the first semiconductor layer, forming a third semiconductor layer of the first type on the second semiconductor layer, and forming a polysilicon layer of the first type on the third semiconductor layer.

Abstract: A semiconductor channel based neuromorphic synapse device 1 including a trap-rich layer may be provided that includes: a first to a third semiconductor regions which are formed on a substrate and are sequentially arranged; a word line which is electrically connected to the first semiconductor region; a trap-rich layer which surrounds the second semiconductor region; and a bit line which is electrically connected to the third semiconductor region. When a pulse with positive (+) voltage is applied to the word line, a concentration of electrons emitted from the trap-rich layer to the second semiconductor region increases and a resistance of the second semiconductor region decreases. When a pulse with negative (?) voltage is applied to the word line, a concentration of electrons trapped in the trap-rich layer from the second semiconductor region increases and the resistance of the second semiconductor region increases.

Abstract: A two-terminal biristor in which a polysilicon emitter layer is inserted and a method of manufacturing the same are provided. The method of manufacturing the two-terminal biristor according to an embodiment of the present disclosure includes forming a first semiconductor layer of a first type on a substrate, forming a second semiconductor layer of a second type on the first semiconductor layer, forming a third semiconductor layer of the first type on the second semiconductor layer, and forming a polysilicon layer of the first type on the third semiconductor layer.

Abstract: A semiconductor channel based neuromorphic synapse device 1 including a trap-rich layer may be provided that includes: a first to a third semiconductor regions which are formed on a substrate and are sequentially arranged; a word line which is electrically connected to the first semiconductor region; a trap-rich layer which surrounds the second semiconductor region; and a bit line which is electrically connected to the third semiconductor region. When a pulse with positive (+) voltage is applied to the word line, a concentration of electrons emitted from the trap-rich layer to the second semiconductor region increases and a resistance of the second semiconductor region decreases. When a pulse with negative (?) voltage is applied to the word line, a concentration of electrons trapped in the trap-rich layer from the second semiconductor region increases and the resistance of the second semiconductor region increases.

Abstract: The present invention provides a reflective type liquid crystal display device and fabricating method thereof, by which resolution is enhanced in a manner of representing two colors from one sub-pixel. The present invention includes a first substrate having a plurality of thin film transistors and a plurality of pixel electrodes within a plurality of sub-pixels defined by a plurality of gate and data lines perpendicularly crossing with each other, respectively, a second substrate assembled to the first substrate to confront, a liquid crystal layer between the first and second substrates, a third substrate assembled to the first substrate to confront, a plurality of reflective electrodes on an inside of the third substrate to correspond to a plurality of the sub-pixels, respectively, and a color filter layer having a plurality of electrophoretic bodies on a plurality of the reflective electrodes wherein each of the electrophoretic bodies is micro-encapsulated with ionic pigment particles.

Abstract: The present invention relates to a wind generator. The wind generator comprises a body installed freely rotatably at a tower, blades installed at a leading end of the body, a gearbox for receiving rotational forces from the blades, and a generator connected to the gearbox for generating electricity. The blades are coupled with a blade angle adjustment unit so that the angles of the blades can be adjusted at predetermined angles according to the directions and velocities of winds. The gearbox comprises a planet gear coupled with a rotational shaft of the blades, a ring gear which has teeth formed on a radially inner surface thereof and engages with the planet gears, and a sun gear which engages with the planet gear and is connected with the generator. Teeth are formed on a radially outer surface of the ring gear so that teeth of a stop gear can be engaged therewith.