Patents by Inventor Jae Hwan CHO
Jae Hwan CHO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240150113Abstract: A photovoltaic power generation module installation support system according to the present invention comprises: a conveyer device, which assembles a plurality of photovoltaic power generation modules into one string and moves same in one direction; and a loading cart including an accommodation space in which the string moved from the conveyer device is loaded in the direction that is horizontal to the ground, wherein the conveyer device includes one or more end stoppers for providing a vertical alignment line of the photovoltaic power generation module first arranged at one end of a conveyor.Type: ApplicationFiled: March 11, 2022Publication date: May 9, 2024Applicant: SAMSUNG C&T CORPORATIONInventors: Dong Shik KIM, Ji Hwan YOON, Kuk Hwan KIM, Jae Seung CHO
-
Patent number: 11976386Abstract: A method of preparing a carbon fiber including: preparing a precursor fiber for preparing a carbon fiber; and stabilizing the precursor fiber. The stabilization of the precursor fiber includes a first stabilization phase, a second stabilization phase, a third stabilization phase, and a fourth stabilization phase, which are set at four different temperatures between a temperature at which heat starts to be generated from the stabilization reaction of the precursor fiber and a temperature at which the generation of heat is maximized. Ozone gas is input while at least one phase of the third stabilization phase and the fourth stabilization phase is carried out.Type: GrantFiled: April 23, 2019Date of Patent: May 7, 2024Assignee: LG CHEM, LTD.Inventors: Jae Gil Choi, Ji Hye Shin, Joon Hee Cho, Su Jin Kim, Ki Hwan Kim, Il Ha Lee, Myung Su Jang
-
Publication number: 20240145346Abstract: A semiconductor device includes a substrate with a conductive pattern. A semiconductor die is electrically connected to the substrate and both the semiconductor die and the substrate are at least partially covered by a package body. In some examples, through-mold vias are formed in the package body to provide electrical signal paths from an exterior surface thereof to the conductive pattern of the substrate. In some examples, through-mold vias are included in the package body to provide electrical signal paths between the semiconductor die and an exterior surface of the package body. In some examples, an interposer is electrically connected to the through-mold vias and may be covered by the package body and/or disposed in spaced relation thereto. In some examples, the interposer may not be electrically connected to the through-mold vias but may have one or more semiconductor dies of the semiconductor device electrically connected thereto.Type: ApplicationFiled: January 8, 2024Publication date: May 2, 2024Applicant: Amkor Technology Singapore Holding Pte. LtdInventors: Dong Joo PARK, Jin Seong KIM, Ki Wook LEE, Dae Byoung KANG, Ho CHOI, Kwang Ho KIM, Jae Dong KIM, Yeon Soo JUNG, Sung Hwan CHO
-
Patent number: 11969397Abstract: The present invention relates to a composition for preventing or treating transplantation rejection or a transplantation rejection disease, comprising a novel compound and a calcineurin inhibitor. A co-administration of the present invention 1) reduces the activity of pathogenic Th1 cells or Th17 cells, 2) increases the activity of Treg cells, 3) has an inhibitory effect against side effects, such as tissue damage, occurring in the sole administration thereof, 4) inhibits various pathogenic pathways, 5) inhibits the cell death of inflammatory cells, and 6) increases the activity of mitochondria, in an in vivo or in vitro allogenic model, a transplantation rejection disease model, a skin transplantation model, and a liver-transplanted patient, and thus inhibits transplantation rejection along with mitigating side effects possibly occurring in the administration of a conventional immunosuppressant alone.Type: GrantFiled: November 7, 2019Date of Patent: April 30, 2024Assignee: THE CATHOLIC UNIVERSITY OF KOREA INDUSTRY-ACADEMIC COOPERATION FOUNDATIONInventors: Mi-La Cho, Dong-Yun Shin, Jong-Young Choi, Chul-Woo Yang, Sung-Hwan Park, Seon-Yeong Lee, Min-Jung Park, Joo-Yeon Jhun, Se-Young Kim, Hyeon-Beom Seo, Jae-Yoon Ryu, Keun-Hyung Cho
-
Patent number: 11961775Abstract: In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The encapsulant can cover the substrate inner sidewall and the device stack and can fill the cavity. Other examples and related methods are disclosed herein.Type: GrantFiled: November 8, 2022Date of Patent: April 16, 2024Assignee: Amkor Technology Singapore Holding Pte. Ltd.Inventors: Gyu Wan Han, Won Bae Bang, Ju Hyung Lee, Min Hwa Chang, Dong Joo Park, Jin Young Khim, Jae Yun Kim, Se Hwan Hong, Seung Jae Yu, Shaun Bowers, Gi Tae Lim, Byoung Woo Cho, Myung Jea Choi, Seul Bee Lee, Sang Goo Kang, Kyung Rok Park
-
Publication number: 20240117211Abstract: A paint composition is prepared by mixing each of an acrylic resin, an acrylic polyol resin, a polycarbonate diol resin, a diisocyanate, a solvent, and an antibacterial agent in appropriate amounts. As a result, the paint composition has improved physical properties and effective antibacterial activities.Type: ApplicationFiled: April 28, 2023Publication date: April 11, 2024Inventors: Hyun Jung Kim, Ho Tak Jeon, Jae Sik Seo, Ji Hwan Park, Dae Joung Cho
-
Patent number: 11945744Abstract: Disclosed are a method and apparatus for reusing wastewater. The method for reusing wastewater disclosed herein includes: generating a mixed wastewater by mixing multiple types of wastewater (S20); performing a first purification by passing the mixed wastewater through a flocculation-sedimentation unit (S40); performing a second purification by passing an effluent of the flocculation-sedimentation unit through a membrane bioreactor (MBR) (S60); performing a third purification by passing an effluent of the MBR through a reverse-osmosis membrane unit (S80); and reusing an effluent of the reverse-osmosis membrane unit as cooling water or industrial water (S100).Type: GrantFiled: April 14, 2023Date of Patent: April 2, 2024Assignees: SAMSUNG ENGINEERING CO., LTD., SAMSUNG ELECTRONICS CO., LTDInventors: Seok Hwan Hong, Dae Soo Park, Seung Joon Chung, Yong Xun Jin, Jae Hyung Park, Jae Hoon Choi, Jae Dong Hwang, Jong Keun Yi, Su Hyoung Cho, Kyu Won Hwang, June Yurl Hur, Je Hun Kim, Ji Won Chun
-
Publication number: 20240098382Abstract: An image processing device including: a decision pixel manager for setting a decision area for a defect candidate pixel, and determining a first decision pixel and a second decision pixel, based on first phase information of pixels included in the decision area with respect to a first modulation frequency of a sensing light source among the pixels; a target pixel determiner for calculating a phase difference between the first decision pixel and the second decision pixel, based on second phase information of the pixels with respect to a second modulation frequency of the sensing light source, and determining the defect candidate pixel as a target pixel, corresponding to that the phase difference exceeds a predetermined reference value; and a phase corrector for changing a phase of the target pixel, based on the phase difference.Type: ApplicationFiled: February 28, 2023Publication date: March 21, 2024Applicant: SK hynix Inc.Inventors: Woo Young JEONG, Ja Min KOO, Tae Hyun KIM, Jae Hwan JEON, Chang Hun CHO
-
Patent number: 11936409Abstract: A transmitter and a receiver are provided. The transmitter includes a processing unit configured to receive a clock signal and a data signal, set a value of a consecutive identical digit (CID) value related to the data signal and generate a modulation signal during a unit interval (UI) based on the data signal and the CID value, and a transmitter driver configured to output output signals having different voltage levels during the unit interval by receiving the modulation signal.Type: GrantFiled: March 1, 2022Date of Patent: March 19, 2024Assignees: Samsung Electronics Co., Ltd., Korea University Research and Business FoundationInventors: Chulwoo Kim, Jonghyuck Choi, Seungwoo Park, Hyun Woo Cho, Tae-Jin Kim, Jae Suk Yu, Kil Hoon Lee, Young Hwan Chang
-
Publication number: 20240068091Abstract: Disclosed is a method of forming an area-selective thin film, the method comprising supplying a nuclear growth retardant to the inside of the chamber in which the substrate is placed, so that the nuclear growth retardant is adsorbed to a non-growth region of the substrate; purging the interior of the chamber; supplying a precursor to the inside of the chamber, so that the precursor is adsorbed to a growth region of the substrate; purging the interior of the chamber; and supplying a reaction material to the inside of the chamber, so that the reaction material reacts with the adsorbed precursor to form the thin film.Type: ApplicationFiled: January 5, 2022Publication date: February 29, 2024Applicant: EGTM Co., Ltd.Inventors: Jae Min KIM, Ha Na KIM, Woong Jin CHOI, Ji Yeon HAN, Ju Hwan JEONG, Hyeon Sik CHO
-
Patent number: 11710788Abstract: A semiconductor device may include active patterns extended in a first direction and spaced apart from each other in the first direction, a device isolation layer defining the active patterns, an insulating structure provided between the active patterns and between the device isolation layer, and a gate structure disposed on the insulating structure and extended in a second direction crossing the first direction. The gate structure may include an upper portion and a lower portion. The lower portion of the gate structure may be enclosed by the insulating structure.Type: GrantFiled: December 6, 2021Date of Patent: July 25, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Kyujin Kim, Hui-Jung Kim, Junsoo Kim, Sangho Lee, Jae-Hwan Cho, Yoosang Hwang
-
Patent number: 11348996Abstract: Disclosed are semiconductor devices including support patterns and methods of fabricating the same. The semiconductor devices may include a plurality of vertical structures on a substrate and a support pattern that contacts sidewalls of the plurality of vertical structures. The support pattern may include a plurality of support holes extending through the support pattern. The plurality of support holes may include a first support hole and a second support hole that are spaced apart from each other, and the first support hole may have a shape or size different from a shape or size of the second support hole.Type: GrantFiled: April 28, 2020Date of Patent: May 31, 2022Inventors: Jae-Hwan Cho, Sangho Lee, Yoosang Hwang
-
Publication number: 20220130950Abstract: Disclosed are semiconductor devices including support patterns and methods of fabricating the same. The semiconductor devices may include a plurality of vertical structures on a substrate and a support pattern that contacts sidewalls of the plurality of vertical structures. The support pattern may include a plurality of support holes extending through the support pattern. The plurality of support holes may include a first support hole and a second support hole that are spaced apart from each other, and the first support hole may have a shape or size different from a shape or size of the second support hole.Type: ApplicationFiled: January 5, 2022Publication date: April 28, 2022Inventors: Jae-Hwan Cho, Sangho Lee, Yoosang Hwang
-
Publication number: 20220093796Abstract: A semiconductor device may include active patterns extended in a first direction and spaced apart from each other in the first direction, a device isolation layer defining the active patterns, an insulating structure provided between the active patterns and between the device isolation layer, and a gate structure disposed on the insulating structure and extended in a second direction crossing the first direction. The gate structure may include an upper portion and a lower portion. The lower portion of the gate structure may be enclosed by the insulating structure.Type: ApplicationFiled: December 6, 2021Publication date: March 24, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Kyujin KIM, Hui-Jung KIM, Junsoo KIM, Sangho LEE, Jae-Hwan CHO, Yoosang HWANG
-
Publication number: 20220013328Abstract: The inventive concept provides a substrate treating apparatus. The substrate treating apparatus includes a process chamber configured to form a treatment space, a gas supply unit configured to supply a process gas into an interior of the process chamber, a plasma generating unit configured to generate plasma from the process gas introduced into the interior of the process chamber, and a substrate support unit provided in the treatment space and configured to support a substrate, the substrate support unit may include a first plate, and a second plate that is adjacent to the first plate, and a gap may be formed between the first plate and the second plate, and a supply pipe is configured to supply a gas into the space defined by the gap.Type: ApplicationFiled: July 1, 2021Publication date: January 13, 2022Applicant: SEMES CO., LTD.Inventors: JE HO KIM, JAE HWAN CHO, TAESUK JUNG
-
Patent number: 11195950Abstract: A semiconductor device may include active patterns extended in a first direction and spaced apart from each other in the first direction, a device isolation layer defining the active patterns, an insulating structure provided between the active patterns and between the device isolation layer, and a gate structure disposed on the insulating structure and extended in a second direction crossing the first direction. The gate structure may include an upper portion and a lower portion. The lower portion of the gate structure may be enclosed by the insulating structure.Type: GrantFiled: December 20, 2019Date of Patent: December 7, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Kyujin Kim, Hui-Jung Kim, Junsoo Kim, Sangho Lee, Jae-Hwan Cho, Yoosang Hwang
-
Publication number: 20210043722Abstract: Disclosed are semiconductor devices including support patterns and methods of fabricating the same. The semiconductor devices may include a plurality of vertical structures on a substrate and a support pattern that contacts sidewalls of the plurality of vertical structures. The support pattern may include a plurality of support holes extending through the support pattern. The plurality of support holes may include a first support hole and a second support hole that are spaced apart from each other, and the first support hole may have a shape or size different from a shape or size of the second support hole.Type: ApplicationFiled: April 28, 2020Publication date: February 11, 2021Inventors: JAE-HWAN CHO, SANGHO LEE, YOOSANG HWANG
-
Publication number: 20210005506Abstract: A semiconductor device may include active patterns extended in a first direction and spaced apart from each other in the first direction, a device isolation layer defining the active patterns, an insulating structure provided between the active patterns and between the device isolation layer, and a gate structure disposed on the insulating structure and extended in a second direction crossing the first direction. The gate structure may include an upper portion and a lower portion. The lower portion of the gate structure may be enclosed by the insulating structure.Type: ApplicationFiled: December 20, 2019Publication date: January 7, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Kyujin KIM, Hui-Jung KIM, Junsoo KIM, Sangho LEE, Jae-Hwan CHO, Yoosang HWANG
-
Patent number: 10636631Abstract: Disclosed is a substrate treating apparatus. The substrate treating apparatus includes a process chamber having a treatment space in the interior thereof, a support unit located in the process chamber to support a substrate, a gas supply unit configured to supply a process gas into the interior of the process chamber, a plasma generating unit including an upper electrode having a through-hole, through which the process gas flows, and a shower head having a hole, through which the process gas is ejected into the treatment space, and an inspection unit configured to inspect a coupling state of the shower head and the upper electrode while an optical fiber is interposed between the upper electrode and the shower head.Type: GrantFiled: August 2, 2018Date of Patent: April 28, 2020Assignee: SEMES CO., LTD.Inventors: Jae Hwan Cho, Hyung Joon Kim
-
Publication number: 20190043699Abstract: Disclosed is a substrate treating apparatus. The substrate treating apparatus includes a process chamber having a treatment space in the interior thereof, a support unit located in the process chamber to support a substrate, a gas supply unit configured to supply a process gas into the interior of the process chamber, a plasma generating unit including an upper electrode having a through-hole, through which the process gas flows, and a shower head having a hole, through which the process gas is ejected into the treatment space, and an inspection unit configured to inspect a coupling state of the shower head and the upper electrode while an optical fiber is interposed between the upper electrode and the shower head.Type: ApplicationFiled: August 2, 2018Publication date: February 7, 2019Inventors: Jae Hwan CHO, Hyung Joon KIM