Abstract: A display device is disclosed that includes a pixel. The pixel includes a first transistor connected between a second node and a third node and including a gate electrode connected to a first node. A first capacitor is formed between the first node and a fourth node. A second capacitor is formed between the fourth node and a first power line. A second transistor is connected between a data line and the fourth node. An eighth transistor is connected between the first power line and the second node. A ninth transistor is connected between the second node and a bias power line. A sixth transistor is connected between the third node and a fifth node. A light emitting element is electrically connected between the fifth node and a second power line. A gate electrode of the eighth transistor and a gate electrode of the sixth transistor are connected to different gate lines.

Abstract: A pixel connected to a first scan line includes a light-emitting element including an anode and a cathode, a first transistor including a first electrode, a second electrode, and a gate electrode connected to a first node, a first capacitor connected between the first node and a second node, a second transistor connected between the second electrode of the first transistor and the first node including a gate electrode connected to the first scan line, a third transistor including a first electrode, a second electrode connected to the second node, and a gate electrode connected to the first scan line, and a fourth transistor including a first electrode connected to a first driving voltage line, a second electrode connected to the first electrode of the first transistor, and a gate electrode connected to the first scan line.

Abstract: A display device includes: a display panel which displays an image corresponding to each of a plurality of frames, and a source driver which drives the display panel. The plurality of frames includes a first frame operating at a first operating frequency, and a second frame operating at a frequency higher than the first operating frequency. The first frame includes a write cycle section, a hold cycle section, and a blank section including a standby section. The source driver operates in a normal driving mode during the write cycle section and the hold cycle section, and operates in a low-power driving mode during the standby section.

Abstract: A pixel includes: a light-emitting element including an anode and a cathode, a first transistor including a first and a second electrode and a gate electrode connected with a first node, a third transistor connected between the second electrode of the first transistor and the first node and including a gate electrode connected with a first scan line, a sixth transistor connected between the second electrode of the first transistor and the anode and including a gate electrode connected with a first emission line, and a seventh transistor connected between the anode and an initialization voltage line and including a gate electrode connected with a second scan line. During an initialization period, the third, sixth, and seventh transistors are turned on such that an initialization voltage from the initialization voltage line is transferred to the gate electrode of the first transistor.

Abstract: A pixel includes: a light emitting element; a first transistor including a gate electrode electrically connected to a first node, a second node to which a first power voltage for driving the light emitting element is to be applied, and a third node electrically connected to the light emitting element; and a bias control transistor configured to be controlled in operating timing thereof by a bias control signal, and configured to switch electrical connection between the second node and a bias power line for transmitting a bias voltage. In one frame period, a voltage level of the bias voltage to be applied to the second node sequentially increases.

Abstract: A pixel includes: a first transistor including a gate electrode electrically connected to a first node, a second node to which a first power voltage for driving the light emitting element is applied, and a third node electrically connected to the light emitting element; a first emission control transistor having an on-off timing controlled by a first emission control signal; and a second emission control transistor having an on-off timing controlled by a second emission control signal. A time interval exists between a time at which the first emission control signal having a turn-on level is input such that a voltage of the second node is dropped from a bias voltage having a voltage level higher than a voltage level of the first power voltage and a time at which the second emission control signal having a turn-on level is input.

Abstract: A peripheral component interconnect express (PCIe) device includes a common function performing operations associated with a PCIe interface according to a function type, the common function being programmable to be a function type selected from a plurality function types, an access identification information controller generating first access identification information for allowing an access to the common function, and providing the first access identification information to an assigned system image to which the common function has been assigned, a data packet receiver receiving a data packet including target identification information indicating a target system image from the target system image, and an access allowance determiner determining whether or not to allow the target system image to access the common function based on the first access identification information and the target identification information.

Abstract: A pixel connected to a first scan line includes a light-emitting element including an anode and a cathode, a first transistor including a first electrode, a second electrode, and a gate electrode connected to a first node, a first capacitor connected between the first node and a second node, a second transistor connected between the second electrode of the first transistor and the first node including a gate electrode connected to the first scan line, a third transistor including a first electrode, a second electrode connected to the second node, and a gate electrode connected to the first scan line, and a fourth transistor including a first electrode connected to a first driving voltage line, a second electrode connected to the first electrode of the first transistor, and a gate electrode connected to the first scan line.

Abstract: A pixel includes: a first transistor including a gate electrode electrically connected to a first node, a second node to which a first power voltage for driving the light emitting element is applied, and a third node electrically connected to the light emitting element; a first emission control transistor having an on-off timing controlled by a first emission control signal; and a second emission control transistor having an on-off timing controlled by a second emission control signal. A time interval exists between a time at which the first emission control signal having a turn-on level is input such that a voltage of the second node is dropped from a bias voltage having a voltage level higher than a voltage level of the first power voltage and a time at which the second emission control signal having a turn-on level is input.

Abstract: A display system includes a host processor configured to provide frame data using a scan order, and a display device including a display panel including pixels and a display panel driver configured to refresh the pixels according using the frame data and to provide the scan order to the host processor.

Abstract: A display device includes: a display panel which displays an image corresponding to each of a plurality of frames, and a source driver which drives the display panel. The plurality of frames includes a first frame operating at a first operating frequency, and a second frame operating at a frequency higher than the first operating frequency. The first frame includes a write cycle section, a hold cycle section, and a blank section including a standby section. The source driver operates in a normal driving mode during the write cycle section and the hold cycle section, and operates in a low-power driving mode during the standby section.

Abstract: A display device includes a display panel which includes first to nth pixel areas arranged in a direction, where n is a natural number greater than or equal to 2, an emission control driver which provides an emission control signal having a plurality of emission cycles corresponding to a number of outputs of a gate-on voltage during a frame period to the first to nth pixel areas, a power supply which generates first to nth bias voltages respectively provided to the first to nth pixel areas, and a timing controller which controls timings when the first to nth bias voltages are supplied to the first to nth pixel areas in a way such that a kth bias voltage is provided with a delay of one emission cycle from a (k?1)th bias voltage, where k is a natural number greater than or equal 2 and less than or equal n.

Abstract: A display device includes a display panel including pixels, and a display panel driver which starts a scan operation in synchronization with an input timing of input image data, performs the scan operation every a scan cycle in one frame, and delays a start of the scan operation of an (N+1)-th frame until the scan operation of an N-th frame ends when the input image data of the (N+1)-th frame is input during the scan operation of the N-th frame, where N is a positive integer.

Abstract: An electronic device includes a display panel which includes a plurality of pixels and displays an image at each of multiple frames, a driving circuit which drives the multiple frames at multiple operating frequencies, a voltage generator which provides a voltage to the display panel, and a drive controller. The drive controller includes a representative frequency calculator which calculates a representative frequency, based on operating frequencies of ‘n’ number of frames before one frame of the multiple frames, and a compensating signal calculator which outputs a compensating signal, based on the representative frequency and a count number in the one frame. The drive controller transmits the compensating signal to the voltage generator, the voltage includes a reference voltage, the voltage generator generates the reference voltage based on the compensating signal, and the voltage generator provides the reference voltage to each of the plurality of pixels.

Abstract: A display device includes: a pixel electrically connected to a data line, a write scan line, an initialization scan line, a compensation scan line, a transmission control line, and an emission control line; a first driving circuit configured to provide a write scan signal to the write scan line and a second driving circuit configured to receive a plurality of clock signals, each of which has a time duration of one unit horizontal period and provide an initialization scan signal, a compensation scan signal, a transmission control signal, and an emission control signal to the initialization scan line, the compensation scan line, the transmission control line, and the emission control line, respectively. Each of the initialization scan signal and the compensation scan signal has an activation interval of one unit horizontal periods or more.

Abstract: A display device includes: a display panel and a panel driver for driving the display panel during a plurality of driving frames whose frequencies are varied. Among the driving frames, a first driving frame having a first frequency includes a first write period, and a second driving frame having a second frequency lower than the first frequency includes a second write period and a variable blank period. The panel driver includes a data driver and a driving controller. Each of the first and second write periods includes N horizontal periods (N is an integer number equal to or greater than 1), each of the N horizontal periods has a first duration, and each of the first and second write periods has a second duration corresponding to N times of the first duration. The driving controller applies a training synchronizing signal to the data driver during the variable blank period.

Abstract: A display device includes a display panel including a pixel which receives a luminance control voltage, a driving controller which receives an input image signal and a control signal and provides an output image signal to the display panel, and a voltage generator which generates the luminance control voltage in response to a voltage control signal from the driving controller. The driving controller determines a current operating frequency based on the control signal, and outputs the voltage control signal based on a difference value between the current operating frequency and a previous operating frequency and an operating time of the previous operating frequency when the current operating frequency is different from the previous operating frequency, where the luminance control voltage is changed from a first voltage level to a second voltage level based on the voltage control signal.

Abstract: A display device includes a light emitting element, a first transistor, and a second transistor connected between the first transistor and the light emitting element and including a gate electrode which receives an emission signal. One frame includes a first period a second period continuous with the first period. An emission off period of the emission signal has a first time duration during the first period, and the emission off period of the emission signal has a second time duration different from the first time duration during the second period.

Abstract: A display device includes a display panel including a pixel and a driving controller to drive the display panel. The driving controller generates a compensating signal, when a first driving frequency of a first frame is determined as being higher than a second driving frequency of a second frame by comparing a first cycle count value of the first frame with a second cycle count value of the second frame subsequent to the first frame.

Abstract: A display device is disclosed that includes a pixel. The pixel includes a first transistor electrode connected between a second node and a third node and including a gate electrode connected to a first node. A first capacitor is formed between the first node and a fourth node. A second capacitor is formed between the fourth node and a first power line. A second transistor is connected between a data line and the fourth node. An eighth transistor is connected between the first power line and the second node. A ninth transistor is connected between the second node and a bias power line. A sixth transistor is connected between the third node and a fifth node. A light emitting element is electrically connected between the fifth node and a second power line. A gate electrode of the eighth transistor and a gate electrode of the sixth transistor are connected to different gate lines.