Patents by Inventor Jae Hyeon Shin

Jae Hyeon Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11882703
    Abstract: Provided herein may be a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device may include a stacked body including a plurality of interlayer insulating layers and a plurality of gate electrodes that are alternately stacked on a substrate, and a plurality of channel structures configured to vertically pass through the stacked body. Each of the plurality of channel structures may include a core insulating layer, a first channel layer, a second channel layer, a tunnel insulating layer, and a charge storage layer that extend vertically towards the substrate. Electron mobility of the first channel layer may be higher than electron mobility of the second channel layer.
    Type: Grant
    Filed: July 15, 2021
    Date of Patent: January 23, 2024
    Assignee: SK hynix Inc.
    Inventors: Sungmook Lim, Dae Hwan Yun, Gil Bok Choi, Jae Hyeon Shin, In Gon Yang, Hyung Jin Choi
  • Patent number: 11776657
    Abstract: A memory device includes a page buffer, a voltage generator, and a test controller. The page buffer is connected to a memory cell through a bit line, and is configured to sense a threshold voltage of the memory cell through a potential of a sensing node electrically connected to the bit line. The voltage generator is configured to generate a test voltage to be applied to the sensing node. The test controller is configured to control the voltage generator to apply the test voltage to the sensing node, and detect a defect of the page buffer, based on a leakage current value of the sensing node.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: October 3, 2023
    Assignee: SK hynix Inc.
    Inventors: In Gon Yang, Tae Ho Kim, Jae Hyeon Shin, Sungmook Lim
  • Patent number: 11615847
    Abstract: A memory device includes a plurality of memory cell strings, a peripheral circuit, and control logic. The plurality of memory cell strings are connected between a bit line and a common source line. The peripheral circuit is configured to perform a channel precharge operation and a program operation for the plurality of memory cell strings. The control logic is configured to control the peripheral circuit to apply a pass voltage to a selected word line among a plurality of word lines connected to the plurality of memory cell strings and to apply a turn-on voltage to a source select line connected to the plurality of memory cell strings, during a portion of a period in which the pass voltage is applied to the selected word line, in the program operation.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: March 28, 2023
    Assignee: SK hynix Inc.
    Inventors: Jae Hyeon Shin, In Gon Yang, Sungmook Lim
  • Patent number: 11482286
    Abstract: A memory device capable of reducing a peak current includes a plurality of memory cell strings each including a plurality of memory cells connected between a common source line and a bit line, a source select line connected between the common source line and the plurality of memory cells, and a drain select line connected between the bit line and the plurality of memory cells. A method for operating the memory device includes: precharging channel regions of a plurality of memory cell strings through a common source line; and setting a bit line voltage applied to the bit line, after starting precharging the channel regions of the plurality of memory cell strings, while the channel regions of the plurality of memory cell strings are being precharged.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: October 25, 2022
    Assignee: SK hynix Inc.
    Inventors: Jae Hyeon Shin, Tae Ho Kim, In Gon Yang, Sungmook Lim
  • Publication number: 20220328106
    Abstract: A memory system includes: a nonvolatile memory device including a plurality of memory blocks each including a plurality of memory cells coupled to a plurality of word lines; and a controller configured to control the nonvolatile memory device to perform a read operation on the plurality of memory blocks, wherein the read operation includes: a first operation of supplying a first voltage level to the plurality of word lines, a second operation of discharging the plurality of word lines to a second voltage level, a third operation of supplying a third voltage level less than the first voltage level to the plurality of word lines, and a fourth operation of discharging the plurality of word lines to a fourth voltage level.
    Type: Application
    Filed: September 2, 2021
    Publication date: October 13, 2022
    Inventors: Sung Hyun HWANG, Jae Hyeon SHIN
  • Patent number: 11462272
    Abstract: There are provided a memory device and an operating method thereof. The memory device includes: a memory block including a plurality of memory cells and a plurality of select transistors; a peripheral circuit for performing a program operation on selected select transistors among the plurality of select transistors in a select transistor program operation; and a control logic for controlling the peripheral circuit to perform the select transistor program operation. The peripheral circuit applies a coupling voltage having a positive potential to a source line of the memory block in the select transistor program operation.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: October 4, 2022
    Assignee: SK hynix Inc.
    Inventors: Hyung Jin Choi, Jae Hyeon Shin, In Gon Yang, Sungmook Lim
  • Patent number: 11462285
    Abstract: The present technology relates to an electronic device. For example, the present technology relates to a memory device and a method of operating the memory device. A memory device according to an embodiment includes a memory cell, a page buffer, and a test performer configured to control the page buffer to sequentially apply a first test voltage and a second test voltage of a level lower than a level of the first test voltage to a sensing node of the page buffer through a bit line, and detect a defect of the sensing node according to whether a potential level of the sensing node is changed.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: October 4, 2022
    Assignee: SK hynix Inc.
    Inventors: Sungmook Lim, In Gon Yang, Jae Hyeon Shin, Hyung Jin Choi
  • Patent number: 11443815
    Abstract: A memory device may include a first sub-block and a second sub-block each including a plurality of select transistors and a plurality of memory cells, a peripheral circuit performing a read operation on data stored in the first sub-block, and a control logic controlling the peripheral circuit to turn on the plurality of select transistors included in each of the first and second sub-blocks and apply a read voltage to a selected word line among a plurality of word lines.
    Type: Grant
    Filed: January 11, 2021
    Date of Patent: September 13, 2022
    Assignee: SK hynix Inc.
    Inventors: Jae Hyeon Shin, Gwi Han Ko, Sung Hun Kim, Gwan Park, Hyun Soo Lee
  • Patent number: 11410731
    Abstract: Provided herein is a semiconductor memory device and a method of operating the same. The semiconductor memory device includes a memory block, a peripheral circuit, and a control logic. The memory block includes a plurality of sub-blocks coupled to a plurality of source select lines, respectively. The peripheral circuit performs a program operation on the memory block. The control logic is configured to control the peripheral circuit to increase a voltage of a common source line that is coupled to the memory block, increase a voltage of at least one source select line, among the plurality of source select lines, to a first voltage level, and set a voltage of a bit line that is coupled to the memory block and increase the voltage of at least one source select line from the first voltage level to a second voltage level.
    Type: Grant
    Filed: February 16, 2021
    Date of Patent: August 9, 2022
    Assignee: SK hynix Inc.
    Inventors: Jae Hyeon Shin, Tae Ho Kim, In Gon Yang, Sungmook Lim
  • Publication number: 20220216231
    Abstract: Provided herein may be a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device may include a stacked body including a plurality of interlayer insulating layers and a plurality of gate electrodes that are alternately stacked on a substrate, and a plurality of channel structures configured to vertically pass through the stacked body. Each of the plurality of channel structures may include a core insulating layer, a first channel layer, a second channel layer, a tunnel insulating layer, and a charge storage layer that extend vertically towards the substrate. Electron mobility of the first channel layer may be higher than electron mobility of the second channel layer.
    Type: Application
    Filed: July 15, 2021
    Publication date: July 7, 2022
    Applicant: SK hynix Inc.
    Inventors: Sungmook LIM, Dae Hwan YUN, Gil Bok CHOI, Jae Hyeon SHIN, In Gon YANG, Hyung Jin CHOI
  • Patent number: 11348641
    Abstract: A memory device and method of operating the same. A memory device includes a memory block, a peripheral circuit, and a program operation controller. The memory block includes a first sub block connected to a first drain select line and a first source select line, and a second sub block connected to a second drain select line and a second source select line, and each of the first sub block and the second sub block is connected to a plurality of word lines and a common source line. The program operation controller controls the peripheral circuit to transfer a precharge voltage to the channel region through the common source line or a plurality of bit lines connected the memory block, and to apply a control voltage to the first and second source select lines at different time points or to apply the control voltage to the first and second drain select lines at different time points in the step of precharging the channel region.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: May 31, 2022
    Assignee: SK hynix Inc.
    Inventors: Jae Hyeon Shin, Gwi Han Ko, Sung Hun Kim, Hyung Jin Choi
  • Publication number: 20220139461
    Abstract: There are provided a memory device and an operating method thereof. The memory device includes: a memory block including a plurality of memory cells and a plurality of select transistors; a peripheral circuit for performing a program operation on selected select transistors among the plurality of select transistors in a select transistor program operation; and a control logic for controlling the peripheral circuit to perform the select transistor program operation. The peripheral circuit applies a coupling voltage having a positive potential to a source line of the memory block in the select transistor program operation.
    Type: Application
    Filed: May 7, 2021
    Publication date: May 5, 2022
    Applicant: SK hynix Inc.
    Inventors: Hyung Jin CHOI, Jae Hyeon SHIN, In Gon YANG, Sungmook LIM
  • Publication number: 20220122687
    Abstract: A memory device includes a page buffer, a voltage generator, and a test controller. The page buffer is connected to a memory cell through a bit line, and is configured to sense a threshold voltage of the memory cell through a potential of a sensing node electrically connected to the bit line. The voltage generator is configured to generate a test voltage to be applied to the sensing node. The test controller is configured to control the voltage generator to apply the test voltage to the sensing node, and detect a defect of the page buffer, based on a leakage current value of the sensing node.
    Type: Application
    Filed: April 23, 2021
    Publication date: April 21, 2022
    Applicant: SK hynix Inc.
    Inventors: In Gon YANG, Tae Ho KIM, Jae Hyeon SHIN, Sungmook LIM
  • Publication number: 20220084612
    Abstract: The present technology relates to an electronic device. For example, the present technology relates to a memory device and a method of operating the memory device. A memory device according to an embodiment includes a memory cell, a page buffer, and a test performer configured to control the page buffer to sequentially apply a first test voltage and a second test voltage of a level lower than a level of the first test voltage to a sensing node of the page buffer through a bit line, and detect a defect of the sensing node according to whether a potential level of the sensing node is changed.
    Type: Application
    Filed: March 10, 2021
    Publication date: March 17, 2022
    Applicant: SK hynix Inc.
    Inventors: Sungmook LIM, In Gon YANG, Jae Hyeon SHIN, Hyung Jin CHOI
  • Publication number: 20220068388
    Abstract: A memory device capable of reducing a peak current includes a plurality of memory cell strings each including a plurality of memory cells connected between a common source line and a bit line, a source select line connected between the common source line and the plurality of memory cells, and a drain select line connected between the bit line and the plurality of memory cells. A method for operating the memory device includes: precharging channel regions of a plurality of memory cell strings through a common source line; and setting a bit line voltage applied to the bit line, after starting precharging the channel regions of the plurality of memory cell strings, while the channel regions of the plurality of memory cell strings are being precharged.
    Type: Application
    Filed: March 3, 2021
    Publication date: March 3, 2022
    Applicant: SK hynix Inc.
    Inventors: Jae Hyeon SHIN, Tae Ho KIM, In Gon YANG, Sungmook LIM
  • Publication number: 20220059167
    Abstract: A memory device includes a plurality of memory cell strings, a peripheral circuit, and control logic, The plurality of memory cell strings are connected between a bit line and a common source line. The peripheral circuit is configured to perform a channel precharge operation and a program operation for the plurality of memory cell strings. The control logic is configured to control the peripheral circuit to apply a pass voltage to a selected word line among a plurality of word lines connected to the plurality of memory cell strings and to apply a turn-on voltage to a source select line connected to the plurality of memory cell strings, during a portion of a period in which the pass voltage is applied to the selected word line, in the program operation.
    Type: Application
    Filed: February 23, 2021
    Publication date: February 24, 2022
    Applicant: SK hynix Inc.
    Inventors: Jae Hyeon SHIN, In Gon YANG, Sungmook LIM
  • Publication number: 20220051723
    Abstract: Provided herein is a semiconductor memory device and a method of operating the same, The semiconductor memory device includes a memory block, a peripheral circuit, and a control logic. The memory block includes a plurality of sub-blocks coupled to a plurality of source select lines, respectively. The peripheral circuit performs a program operation on the memory block. The control logic is configured to control the peripheral circuit to increase a voltage of a common source line that is coupled to the memory block, increase a voltage of at least one source select line, among the plurality of source select lines, to a first voltage level, and set a voltage of a bit line that is coupled to the memory block and increase the voltage of at least one source select line from the first voltage level to a second voltage level.
    Type: Application
    Filed: February 16, 2021
    Publication date: February 17, 2022
    Applicant: SK hynix Inc.
    Inventors: Jae Hyeon SHIN, Tae Ho KIM, In Gon YANG, Sungmook LIM
  • Publication number: 20220028462
    Abstract: A memory device may include a first sub-block and a second sub-block each including a plurality of select transistors and a plurality of memory cells, a peripheral circuit performing a read operation on data stored in the first sub-block, and a control logic controlling the peripheral circuit to turn on the plurality of select transistors included in each of the first and second sub-blocks and apply a read voltage to a selected word line among a plurality of word lines.
    Type: Application
    Filed: January 11, 2021
    Publication date: January 27, 2022
    Inventors: Jae Hyeon SHIN, Gwi Han KO, Sung Hun KIM, Gwan PARK, Hyun Soo LEE
  • Patent number: 11056176
    Abstract: A memory device having improved read reliability includes: first blocks coupled to a first global line group and second blocks coupled to a second global line group; a voltage generator configured to generate an operating voltage for an operation performed on the first blocks and the second blocks; a block decoder configured to generate a block select signal for selecting a memory block on which a main operation is to be performed from among the first blocks as a selected block; and a block voltage controller configured to control the block decoder and the voltage generator to: perform a channel initializing operation of discharging channel regions of the selected block and a shared block which is selected from among the second blocks according to the block select signal; and perform a word line floating operation on the selected block and the shared block after the channel initializing operation.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: July 6, 2021
    Assignee: SK hynix Inc.
    Inventor: Jae Hyeon Shin
  • Publication number: 20210158871
    Abstract: A memory device includes a memory block, a peripheral circuit, and a program operation controller. The memory block includes a first sub block connected to a first drain select line and a first source select line, and a second sub block connected to a second drain select line and a second source select line, and is connected to a plurality of word lines and a common source line. The program operation controller controls the peripheral circuit to transfer a precharge voltage to the channel region through the common source line or a plurality of bit lines connected the memory block, and to apply a control voltage to the first and second source select lines at different time points or to apply the control voltage to the first and second drain select lines at different time points in the step of precharging the channel region.
    Type: Application
    Filed: April 23, 2020
    Publication date: May 27, 2021
    Inventors: Jae Hyeon SHIN, Gwi Han KO, Sung Hun KIM, Hyung Jin CHOI