Patents by Inventor Jaehyeong HONG

Jaehyeong HONG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Data sampling circuit and data transmitter circuit
    Patent number: 11972837
    Abstract: A data sampling circuit may include a pattern detection circuit configured to generate a slow signal by detecting a pattern of multibit data including input data, and a sampling circuit configured to sample the input data during an activation period of a sampling clock and having an operating speed of the sampling circuit reduced when the slow signal is activated.
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: April 30, 2024
    Assignee: SK hynix Inc.
    Inventors: Inseok Kong, Jaehyeong Hong, Min Su Kim
  • Input/output circuit, operation method thereof and data processing system including the same
    Patent number: 11962300
    Abstract: An input/output circuit may include an input circuit, an amplifier circuit and a precharging circuit. The input circuit may load differential input data to setup nodes based on a data strobe clock. The amplifier circuit may compare and amplify the data that is loaded to the setup nodes and configured to output the amplified data. The precharging circuit may precharge the setup nodes based on the data strobe clock and the differential input data.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: April 16, 2024
    Assignee: SK hynix Inc.
    Inventors: Jaehyeong Hong, Yo Han Jeong, Jin Ha Hwang, Junseo Jang
  • BUFFER CIRCUIT CAPABLE OF REDUCING NOISE
    Publication number: 20240097685
    Abstract: A buffer circuit includes a power control circuit, an inverting circuit, and a voltage adjustment circuit. The power control circuit is configured to provide voltages based on an input signal and a mode signal, and the inverting circuit is configured to receive and invert the voltages to generate an output signal. The voltage adjustment circuit is configured to adjust voltage levels based on the mode signal and the output signal.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 21, 2024
    Applicant: SK hynix Inc.
    Inventors: Jin Ha HWANG, Soon Sung AN, Junseo JANG, Jaehyeong HONG
  • Buffer circuit capable of reducing noise
    Patent number: 11843373
    Abstract: A buffer circuit includes a power control circuit, an inverting circuit, and a voltage adjustment circuit. The power control circuit is configured to provide voltages based on an input signal and a mode signal, and the inverting circuit is configured to receive and invert the voltages to generate an output signal. The voltage adjustment circuit is configured to adjust voltage levels based on the mode signal and the output signal.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: December 12, 2023
    Assignee: SK hynix Inc.
    Inventors: Jin Ha Hwang, Soon Sung An, Junseo Jang, Jaehyeong Hong
  • Memory device for correcting pulse duty and memory system including the same
    Patent number: 11837310
    Abstract: The present disclosure relates to a memory device for correcting a pulse duty ratio and a memory system including the same, and relates to a memory device which corrects the duty ratio of a primary pulse of a memory device control signal, and a memory system including the same.
    Type: Grant
    Filed: January 5, 2022
    Date of Patent: December 5, 2023
    Assignee: SK hynix Inc.
    Inventors: Jaehyeong Hong, In Seok Kong, Gwan Woo Kim, Jae Young Park, Kwan Su Shon, Soon Sung An, Daeho Yang, Sung Hwa Ok, Junseo Jang, Yo Han Jeong, Eun Ji Choi
  • DATA SAMPLING CIRCUIT AND DATA TRANSMITTER CIRCUIT
    Publication number: 20230298644
    Abstract: A data sampling circuit may include a pattern detection circuit configured to generate a slow signal by detecting a pattern of multibit data including input data, and a sampling circuit configured to sample the input data during an activation period of a sampling clock and having an operating speed of the sampling circuit reduced when the slow signal is activated.
    Type: Application
    Filed: June 23, 2022
    Publication date: September 21, 2023
    Inventors: Inseok KONG, Jaehyeong HONG, Min Su Kim
  • MEMORY DEVICE FOR CORRECTING PULSE DUTY AND MEMORY SYSTEM INCLUDING THE SAME
    Publication number: 20230056686
    Abstract: The present disclosure relates to a memory device for correcting a pulse duty ratio and a memory system including the same, and relates to a memory device which corrects the duty ratio of a primary pulse of a memory device control signal, and a memory system including the same.
    Type: Application
    Filed: January 5, 2022
    Publication date: February 23, 2023
    Inventors: Jaehyeong HONG, In Seok KONG, Gwan Woo KIM, Jae Young PARK, Kwan Su SHON, Soon Sung AN, Daeho YANG, Sung Hwa OK, Junseo JANG, Yo Han JEONG, Eun Ji CHOI
  • BUFFER CIRCUIT CAPABLE OF REDUCING NOISE
    Publication number: 20220416790
    Abstract: A buffer circuit includes a power control circuit, an inverting circuit, and a voltage adjustment circuit. The power control circuit is configured to provide voltages based on an input signal and a mode signal, and the inverting circuit is configured to receive and invert the voltages to generate an output signal. The voltage adjustment circuit is configured to adjust voltage levels based on the mode signal and the output signal.
    Type: Application
    Filed: October 29, 2021
    Publication date: December 29, 2022
    Applicant: SK hynix Inc.
    Inventors: Jin Ha HWANG, Soon Sung AN, Junseo JANG, Jaehyeong HONG
  • INPUT/OUTPUT CIRCUIT, OPERATION METHOD THEREOF AND DATA PROCESSING SYSTEM INCLUDING THE SAME
    Publication number: 20220123736
    Abstract: An input/output circuit may include an input circuit, an amplifier circuit and a precharging circuit. The input circuit may load differential input data to setup nodes based on a data strobe clock. The amplifier circuit may compare and amplify the data that is loaded to the setup nodes and configured to output the amplified data. The precharging circuit may precharge the setup nodes based on the data strobe clock and the differential input data.
    Type: Application
    Filed: January 27, 2021
    Publication date: April 21, 2022
    Applicant: SK hynix Inc.
    Inventors: Jaehyeong HONG, Yo Han JEONG, Jin Ha HWANG, Junseo JANG