Abstract: Disclosed is an output signal buffer circuit of semiconductor memory devices comprises: a plurality of buffer groups each comprising a plurality of output buffers grouped into unit group, in which each output buffer comprises a pull up transistor and a pull down transistor connected between a power supply voltage and ground in series; driving means for sequentially driving respective buffer groups according to internal control signals; and control signal generating means for producing the internal control signals for sequentially driving said buffer groups to said driving means in accordance with an external control signal.

Abstract: A row decoder for a semiconductor memory device having a plurality of cell strings with a plurality of memory cells, is disclosed. The row decoder includes: selection line decoders that respectively correspond to the cell strings, and output a signal for selecting one of the corresponding cell strings; a word line decoder outputting word-line selection signals used for selecting a corresponding memory cell's word line among the memory cells of the selected one of the cell strings; and a plurality of switching circuits that correspond to the cell strings, and transmit each word-line selection signal, outputted from the word line decoder, to a corresponding memory cell of a cell string selected by one selection signal.

Abstract: The present invention discloses a mask ROM having a pipeline structure using simple latch circuits. Accordingly, the mask ROM according to the present invention improves its speed and guarantees the security of the output data, by proving a clock generator and a plurality of latch circuit for storing the outputs from each of the element therein, being synchronized with the internal clock signal from the clock generating means.

Abstract: A sense amplifier of a semiconductor memory device includes: a precharge section for precharging the dummy line and bit line with a required voltage by means of an equalizer signal transferred from an external; a data sensing section for receiving and latching voltage of the bit line and voltage of the dummy lines as first and second input signals, respectively, by means of a sense amplifier enable signal transferred from the external, thereby sensing data from the memory cell and generating it as an output signal; a precharge enable section for disabling the precharge section by means of the sense amplifier enable signal transferred from the external when in a data sensing operation or for enabling the precharge section when not in a data sensing operation; and a data sensing enable section for transmitting the voltage of the bit line and the voltage of dummy line as first and second input signals, respectively, to the data sensing section according to the sense amplifier enable signal from the external depe

Abstract: A column repair circuit for a semiconductor memory having an input/output selection circuit for inputting a control signal, selecting a bit line and a bit bar line corresponding to a faulty memory cell and replacing the selected bit line and bit bar line with a spare bit line and a spare bit bar line. The input/output selection circuit includes an input stage for inputting the control signal, a spare bit line and a spare bit bar line, and a plurality of fuses each having one side connected to the input stage and other side connected to a plurality of resistors. The other side of the resistors are connected to ground for outputting the output signals. The input/output selection circuit further has a plurality of n-channel MOSFETs each including a gate connected to each of the other stages of the plurality of fuses via the resistors in a 2 to 1 manner for inputting the output signals.