Patents by Inventor Jae Hyun Jeon

Jae Hyun Jeon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220302458
    Abstract: Disclosed are a flexible electrode substrate including a porous electrode, a method for manufacturing the flexible electrode substrate, and an energy storage element including the flexible electrode substrate. The flexible electrode substrate can be attached to various objects due to the excellent electrochemical properties and the adhesive properties thereof and thus is very useful. In particular, since the flexible electrode substrate can be used as an electrode of an energy storage element, an energy storage element including the flexible electrode substrate can be attached to various objects and thus can be used as a sticker-type energy storage element. In addition, the flexible electrode substrate can be easily manufactured by transfer method using a difference in adhesive strength and thus allows a simple manufacturing process thereof. Furthermore, electrodes having various patterns can be manufactured with high level of efficiency through simple adjustment of the manufacturing process.
    Type: Application
    Filed: August 13, 2019
    Publication date: September 22, 2022
    Applicant: KOREA INSTITUTE OF ENERGY RESEARCH
    Inventors: Ha Na YOON, Chung Yul YOO, Sang Hyun PARK, Jung Joon YOO, Young A LEE, Jae Hyun JEON, Kyu Yeon JANG
  • Patent number: 9525363
    Abstract: Disclosed is a method for voltage dip compensation of inverter, the method including reducing an output frequency of an inverter to obtain a regenerative energy when it is determined that power failure has occurred during the inverter operation, adjusting increase/decrease of inverter output frequency in response to size of exceeding current and voltage based on an output current and DC-link voltage of the inverter, increasing the inverter output frequency in order to prevent excessive current flow when power restoration occurs at a power failure state, and returning to a speed prior to the momentary voltage dip by gradually increasing the inverter output frequency in a state where the inverter output frequency does not exceed an over-current limit by monitoring the inverter output frequency.
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: December 20, 2016
    Assignee: LSIS CO., LTD.
    Inventor: Jae Hyun Jeon
  • Publication number: 20150357936
    Abstract: Disclosed is a method for voltage dip compensation of inverter, the method including reducing an output frequency of an inverter to obtain a regenerative energy when it is determined that power failure has occurred during the inverter operation, adjusting increase/decrease of inverter output frequency in response to size of exceeding current and voltage based on an output current and DC-link voltage of the inverter, increasing the inverter output frequency in order to prevent excessive current flow when power restoration occurs at a power failure state, and returning to a speed prior to the momentary voltage dip by gradually increasing the inverter output frequency in a state where the inverter output frequency does not exceed an over-current limit by monitoring the inverter output frequency.
    Type: Application
    Filed: June 9, 2015
    Publication date: December 10, 2015
    Applicant: LSIS CO., LTD.
    Inventor: Jae Hyun JEON
  • Patent number: 9093892
    Abstract: Provided is an apparatus and method for controlling medium voltage inverter, whereby a frequency outputted by the medium voltage inverter is fixed, in a case an instantaneous power interrupt occurs while the medium voltage inverter drives a motor, and a voltage level of an AC power generated by the medium voltage inverter is reduced and outputted in response to a predetermined deceleration slope to control the medium voltage inverter.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: July 28, 2015
    Assignee: LSIS Co., Ltd.
    Inventor: Jae Hyun Jeon
  • Patent number: 8970159
    Abstract: Provided are a method for compensating instantaneous power failure in medium voltage inverter and a medium voltage inverter system by using the same, the method for compensating instantaneous power failure in medium voltage inverter including a plurality of power cells supplying a phase voltage to a motor by being connected to the motor in series, the method including decreasing an output frequency of the plurality of power cells by as much as a predetermined value at a relevant point where an input voltage of the plurality of power cells is less than a reference value, decreasing the output frequency at a predetermined deceleration gradient, and maintaining the output frequency during restoration of input voltage as long as a predetermined time, in a case the input voltage is restored.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: March 3, 2015
    Assignee: LSIS Co., Ltd.
    Inventors: Jung Muk Choi, Seung Ho Na, Jae Hyun Jeon, Sung Guk Ahn
  • Publication number: 20130076285
    Abstract: Provided are a method for compensating instantaneous power failure in medium voltage inverter and a medium voltage inverter system by using the same, the method for compensating instantaneous power failure in medium voltage inverter including a plurality of power cells supplying a phase voltage to a motor by being connected to the motor in series, the method including decreasing an output frequency of the plurality of power cells by as much as a predetermined value at a relevant point where an input voltage of the plurality of power cells is less than a reference value, decreasing the output frequency at a predetermined deceleration gradient, and maintaining the output frequency during restoration of input voltage as long as a predetermined time, in a case the input voltage is restored.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 28, 2013
    Applicant: LSIS CO., LTD.
    Inventors: JUNG MUK CHOI, SEUNG HO NA, JAE HYUN JEON, SUNG GUK AHN
  • Patent number: 8361177
    Abstract: Disclosed is a polishing slurry, particularly, a slurry for chemical mechanical polishing, which is used in a chemical mechanical polishing process for flattening a semiconductor laminate. More particularly, the present invention provides a method of producing a slurry which has high removal selectivity to a nitride layer used as a barrier film in a shallow trench isolation CMP process needed to fabricate ultra highly integrated semiconductors of 256 mega D-RAM or more (Design rule of 0.13 ?m or less) and which decreases the occurrence of scratches on a flattened surface, and a method of polishing a substrate using the same.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: January 29, 2013
    Assignees: K.C. Tech Co., Ltd., IUCF-HYU
    Inventors: Dae Hyeong Kim, Seok Min Hong, Jae Hyun Jeon, Un Gyu Park, Jea Gun Park, Yong Kuk Kim
  • Publication number: 20130020976
    Abstract: Provided is an apparatus and method for controlling medium voltage inverter, whereby a frequency outputted by the medium voltage inverter is fixed, in a case an instantaneous power interrupt occurs while the medium voltage inverter drives a motor, and a voltage level of an AC power generated by the medium voltage inverter is reduced and outputted in response to a predetermined deceleration slope to control the medium voltage inverter.
    Type: Application
    Filed: July 17, 2012
    Publication date: January 24, 2013
    Applicant: LSIS CO., LTD.
    Inventor: Jae Hyun JEON
  • Patent number: 8345455
    Abstract: The present invention relates to a control device and a control method of a high voltage inverter capable of automatically and accurately setting up neutral point information at a master controller and a plurality of cell controllers of the high voltage inverter, wherein a master controller determines information of neutral point set up to itself and performs a communication with the cell controllers each disposed at each of a plurality of U phase unit cells, a plurality of V phase unit cells and a plurality of W phase unit cells to determine the neutral point information preset on the cell controllers and to detect a cell controller set up with neutral point information different from that of the master controller, and to correct the neutral point information of the detected relevant cell controller using the neutral point information set up in the master controller, thereby operating the high voltage inverter.
    Type: Grant
    Filed: February 22, 2010
    Date of Patent: January 1, 2013
    Assignee: LS Industrial Systems Co., Ltd.
    Inventor: Jae Hyun Jeon
  • Publication number: 20110050199
    Abstract: The present invention relates to a control device and a control method of a high voltage inverter capable of automatically and accurately setting up neutral point information at a master controller and a plurality of cell controllers of the high voltage inverter, wherein a master controller determines information of neutral point set up to itself and performs a communication with the cell controllers each disposed at each of a plurality of U phase unit cells, a plurality of V phase unit cells and a plurality of W phase unit cells to determine the neutral point information preset on the cell controllers and to detect a cell controller set up with neutral point information different from that of the master controller, and to correct the neutral point information of the detected relevant cell controller using the neutral point information set up in the master controller, thereby operating the high voltage inverter.
    Type: Application
    Filed: February 22, 2010
    Publication date: March 3, 2011
    Inventor: Jae Hyun JEON
  • Publication number: 20090133336
    Abstract: Disclosed is a polishing slurry, particularly, a slurry for chemical mechanical polishing, which is used in a chemical mechanical polishing process for flattening a semiconductor laminate. More particularly, the present invention provides a method of producing a slurry which has high removal selectivity to a nitride layer used as a barrier film in a shallow trench isolation CMP process needed to fabricate ultra highly integrated semiconductors of 256 mega D-RAM or more (Design rule of 0.13 ?m or less) and which decreases the occurrence of scratches on a flattened surface, and a method of polishing a substrate using the same.
    Type: Application
    Filed: December 11, 2008
    Publication date: May 28, 2009
    Applicants: K.C. TECH CO., LTD., IUCF-HYU
    Inventors: Dae Hyeong Kim, Seok Min Hong, Jae Hyun Jeon, Un Gyu Paik, Jea Gun Park, Yong Kuk Kim
  • Publication number: 20090100765
    Abstract: Disclosed is a polishing slurry, particularly, a slurry for chemical mechanical polishing, which is used in a chemical mechanical polishing process for flattening a semiconductor laminate. More particularly, the present invention provides a method of producing a slurry which has high removal selectivity to a nitride layer used as a barrier film in a shallow trench isolation CMP process needed to fabricate ultra highly integrated semiconductors of 256 mega D-RAM or more (Design rule of 0.13 ?m or less) and which decreases the occurrence of scratches on a flattened surface, and a method of polishing a substrate using the same.
    Type: Application
    Filed: December 11, 2008
    Publication date: April 23, 2009
    Applicants: K.C. TECH CO., LTD., IUCF-HYU
    Inventors: Dae Hyeong Kim, Seok Min Hong, Jae Hyun Jeon, Un Gyu Paik, Jea Gun Park, Yong Kuk Kim
  • Patent number: 7470295
    Abstract: Disclosed herein is a polishing slurry for chemical mechanical polishing. The polishing slurry comprises polishing particles, which have a particle size distribution including separated fine and large polishing particle peaks. The polishing slurry also comprises polishing particles, which have a median size of 50-150 nm. The present invention provides the slurry having an optimum polishing particle size, in which the polishing particle size is controlled and which is useful to produce semiconductors having fine design rules by changing the production conditions of the slurry. The present invention also provides the polishing slurry and a method of producing the same, in which a desirable CMP removal rate is assured and scratches are suppressed by controlling a polishing particle size distribution, and a method of polishing a substrate.
    Type: Grant
    Filed: March 11, 2005
    Date of Patent: December 30, 2008
    Assignees: K.C. Tech Co., Ltd., IUCF-HYU
    Inventors: Dae Hyung Kim, Seok Min Hong, Jae Hyun Jeon, Ho Seong Kim, Hyun Soo Park, Un Gyu Paik, Jae Gun Park, Yong Kuk Kim
  • Patent number: 7364600
    Abstract: Disclosed herein is a polishing slurry and a method of producing the same. The polishing slurry has high selectivity in terms of a polishing speed of an oxide layer to that of a nitride layer used in CMP of an STI process which is essential to produce ultra highly integrated semiconductors having a design rule of 256 mega D-RAM or more, for example, a design rule of 0.13 ?m or less. A method and a device for pre-treating polishing particles, a dispersing device and a method of operating the dispersing device, a method of adding a chemical additive and an amount added, and a device for transferring samples are properly employed to produce a high performance nano ceria slurry essential to CMP for a process of producing ultra highly integrated semiconductors of 0.13 ?m or less, particularly, the STI process.
    Type: Grant
    Filed: May 11, 2005
    Date of Patent: April 29, 2008
    Assignees: K.C. Tech Co., Ltd., IUCF-HYU
    Inventors: Dae Hyeong Kim, Seok Min Hong, Jae Hyun Jeon, Ho Seong Kim, Hyun Soo Park, Un Gyu Paik, Jae Gun Park, Yong Kuk Kim