Patents by Inventor Jae-hyun Phee
Jae-hyun Phee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20180108540Abstract: A method of manufacturing a semiconductor package including forming a photoresist pattern on a first surface of an interposer substrate. The interposer substrate includes an electrode zone and a scribe line zone. The interposer substrate is etched using the photoresist pattern as a mask to form a first opening and a second opening respectively on the electrode zone and the scribe line zone. An insulation layer and a conductive layer are formed on the first surface of the interposer substrate. A width of the second opening is smaller than a width of the first opening. The insulation layer contacts each of the first surface of the interposer substrate, an inner surface of the first opening, and an inner surface of the second opening.Type: ApplicationFiled: June 29, 2017Publication date: April 19, 2018Inventors: Jae-Hyun Phee, Ho-Jin Lee, Taeseong Kim, Kwangjin Moon, Jin Ho An, Naein Lee
-
Patent number: 8778776Abstract: Provided is a method of forming a semiconductor package including providing a substrate having a first side and an opposite second side and providing a wafer having a plurality of semiconductor chips, each of the semiconductor chips having a conductive pad, wherein at least one of the substrate and the wafer includes a seed pattern. The first side of the substrate is bonded to the wafer with the conductive pad positioned adjacent to the first side of the substrate and the seed pattern positioned between the conductive pad and the first side of the substrate. A through hole is then formed penetrating the substrate from the second side of the substrate to expose the seed pattern. A through electrode is formed in the through hole using the seed pattern as a seed. Corresponding devices are also provided.Type: GrantFiled: July 21, 2011Date of Patent: July 15, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Ju-il Choi, Kyu-Ha Lee, Jae-hyun Phee, Jung-Hwan Kim, Tae Hong Min
-
Publication number: 20140145327Abstract: Semiconductor devices and methods for fabricating the same are provided. For example, the semiconductor device includes a substrate, a first contact pad formed on the substrate, an insulation layer formed on the substrate and including a first opening which exposes the first contact pad, a first bump formed on the first contact pad and electrically connected to the first contact pad, and a reinforcement member formed on the insulation layer and adjacent to a side surface of the first lower bump. The first bump includes a first lower bump and a first upper bump, which are sequentially stacked on the first contact pad.Type: ApplicationFiled: October 23, 2013Publication date: May 29, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyung-Jun JEON, Jae-Hyun PHEE, Byung-Lyul PARK, Ji-Soon PARK, Jeong-Gi JIN
-
Patent number: 8637989Abstract: A semiconductor device includes a semiconductor substrate and a via electrode. The via electrode has a first portion on the substrate and extends towards the substrate and has a plurality of spikes that extends from the first portion into the substrate, each of the spikes being spaced apart form one another.Type: GrantFiled: August 8, 2012Date of Patent: January 28, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Ho-jin Lee, Hyun-soo Chung, Chang-seong Jeon, Sang-sick Park, Jae-hyun Phee
-
Patent number: 8586477Abstract: A semiconductor apparatus having a through electrode, a semiconductor package, and a method of manufacturing the semiconductor package are provided. The method of includes preparing a substrate including a buried via, the buried via having a first surface at a first end, and the buried via extending from a first substrate surface of the substrate into the substrate; planarizing a second substrate surface of the substrate opposite the first substrate surface to form a through via by exposing a second via surface at a second end of the buried via opposite the first end; forming a conductive capping layer on the exposed second via surface of the through via; and recessing the second substrate surface so that at least a first portion of the through via extends beyond the second substrate surface.Type: GrantFiled: August 1, 2011Date of Patent: November 19, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Se-young Jeong, Ho-jin Lee, Ho-geon Song, Jae-hyun Phee
-
Patent number: 8575760Abstract: A semiconductor device includes a substrate having a first surface and an opposite second surface. An electrode extends within the substrate towards the first surface and has a protruding portion extending from the first surface. A supporting portion extends from the first surface of the substrate to a sidewall of the protruding portion and supports the protruding portion.Type: GrantFiled: November 23, 2011Date of Patent: November 5, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-hyun Phee, Uihyouong Lee, Ju-il Choi, Jung-Hwan Kim
-
Patent number: 8564102Abstract: A semiconductor device and a method of fabricating a semiconductor device. The semiconductor device includes an interlayer insulation layer pattern, a metal wire pattern exposed by a passage formed by a via hole formed in the interlayer insulation layer pattern to input and output an electrical signal, and a plated layer pattern directly contacting the metal wire pattern and filling the via hole. The method includes forming an interlayer insulation layer having a metal wire pattern to input and output an electrical signal formed therein, forming a via hole to define a passage that extends through the interlayer insulation layer until at least a part of the metal wire pattern is exposed, and forming a plated layer pattern to fill the via hole and to directly contact the metal wire pattern by using the metal wire pattern exposed through the via hole as a seed metal layer.Type: GrantFiled: May 16, 2011Date of Patent: October 22, 2013Assignee: SAMSUNG Electronics Co., Ltd.Inventors: Ju-il Choi, Jae-hyun Phee, Kyu-ha Lee, Ho-jin Lee, Son-kwan Hwang
-
Patent number: 8492902Abstract: Provided is a semiconductor device. The semiconductor device may include a substrate and a stacked insulation layer on a sidewall of an opening which penetrates the substrate. The stacked insulation layer can include at least one first insulation layer and at least one second insulation layer whose dielectric constant is different than that of the first insulation layer. One insulation layer may be a polymer and one insulation layer may be a silicon based insulation layer. The insulation layers may be uniform in thickness or may vary as a distance from the substrate changes.Type: GrantFiled: March 16, 2011Date of Patent: July 23, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Ho-Jin Lee, SeYoung Jeong, Jae-hyun Phee, Jung-Hwan Kim, Tae Hong Min
-
Publication number: 20120299194Abstract: A semiconductor device includes a semiconductor substrate and a via electrode. The via electrode has a first portion on the substrate and extends towards the substrate and has a plurality of spikes that extends from the first portion into the substrate, each of the spikes being spaced apart form one another.Type: ApplicationFiled: August 8, 2012Publication date: November 29, 2012Inventors: Ho-jin Lee, Hyun-soo Chung, Chang-seong Jeon, Sang-sick Park, Jae-hyun Phee
-
Publication number: 20120292195Abstract: An apparatus for electroplating a semiconductor device includes a plating bath accommodating a plating solution, and a paddle in the plating bath, the paddle including a plurality of holes configured to pass the plating solution through the paddle toward a substrate, and a plating solution flow reinforcement portion configured to selectively reinforce a flow of the plating solution to a predetermined area of the substrate, the predetermined area of the substrate being an area requiring a relatively increased supply of metal ions of the plating solution.Type: ApplicationFiled: April 3, 2012Publication date: November 22, 2012Inventors: Ui Hyoung LEE, Ju-Il Choi, Jae-Hyun Phee, Dong Hyeon Jang, Jeong-Woo Park
-
Publication number: 20120199981Abstract: A semiconductor device includes a first device including a first substrate and a first external connection terminal for connecting outside the first device; a second device stacked on the first device, the second device including a second substrate and a second external connection terminal for connecting outside the second device; an adhesive pattern disposed between the first device and second device, the adhesive pattern disposed in locations other than locations where the first external connection terminal and second external connection terminal are disposed, and the adhesive pattern causing the first device and second device, when stacked, to be spaced apart by a predetermined distance; and a plated layer disposed between and electrically and physically connecting the first external connection terminal and the second external connection terminal.Type: ApplicationFiled: February 2, 2012Publication date: August 9, 2012Inventors: Se-young Jeong, Ho-geon Song, Ju-il Choi, Jae-hyun Phee
-
Publication number: 20120133041Abstract: Some embodiments provide a semiconductor device including a substrate having a first surface and an opposite second surface. An electrode extends within the substrate towards the first surface and has a protruding portion extending from the first surface. A supporting portion extends from the first surface of the substrate to a sidewall of the protruding portion that supports the protruding portion. Methods of fabricating the same are also provided.Type: ApplicationFiled: November 23, 2011Publication date: May 31, 2012Inventors: Jae-hyun Phee, Uihyouong Lee, Ju-il Choi, Jung-Hwan Kim
-
Publication number: 20120083097Abstract: Provided is a method of forming a semiconductor package including providing a substrate having a first side and an opposite second side and providing a wafer having a plurality of semiconductor chips, each of the semiconductor chips having a conductive pad, wherein at least one of the substrate and the wafer includes a seed pattern. The first side of the substrate is bonded to the wafer with the conductive pad positioned adjacent to the first side of the substrate and the seed pattern positioned between the conductive pad and the first side of the substrate. A through hole is then formed penetrating the substrate from the second side of the substrate to expose the seed pattern. A through electrode is formed in the through hole using the seed pattern as a seed. Corresponding devices are also provided.Type: ApplicationFiled: July 21, 2011Publication date: April 5, 2012Inventors: Ju-il Choi, Kyu-Ha Lee, Jae-Hyun Phee, Jung-Hwan Kim, Tae Hong Min
-
Publication number: 20120074584Abstract: Provided is a semiconductor device. The semiconductor device may include a substrate and a stacked insulation layer on a sidewall of an opening which penetrates the substrate. The stacked insulation layer can include at least one first insulation layer and at least one second insulation layer whose dielectric constant is different than that of the first insulation layer. One insulation layer may be a polymer and one insulation layer may be a silicon based insulation layer. The insulation layers may be uniform in thickness or may vary as a distance from the substrate changes.Type: ApplicationFiled: March 16, 2011Publication date: March 29, 2012Inventors: Ho-Jin LEE, SeYoung Jeong, Jae-hyun Phee, Jung-Hwan Kim, Tae Hong Min
-
Patent number: 8129840Abstract: A semiconductor package and a method of manufacturing the semiconductor package. The semiconductor package include a substrate including a plurality of pads and a plurality of bumps evenly disposed on an entire region of the substrate regardless of an arrangement of the plurality of pads. According to the present invention, a simplification of a process can be accomplished, a cost of a process can be reduced, reliability can be improved and an under-filling can become easy.Type: GrantFiled: July 15, 2009Date of Patent: March 6, 2012Assignee: SAMSUNG Electronics Co., Ltd.Inventors: Chajea Jo, Uihyoung Lee, Jae-hyun Phee, Jeong-Woo Park, Ha-Young Yim
-
Publication number: 20120028412Abstract: A semiconductor apparatus having a through electrode, a semiconductor package, and a method of manufacturing the semiconductor package are provided. The method of includes preparing a substrate including a buried via, the buried via having a first surface at a first end, and the buried via extending from a first substrate surface of the substrate into the substrate; planarizing a second substrate surface of the substrate opposite the first substrate surface to form a through via by exposing a second via surface at a second end of the buried via opposite the first end; forming a conductive capping layer on the exposed second via surface of the through via; and recessing the second substrate surface so that at least a first portion of the through via extends beyond the second substrate surface.Type: ApplicationFiled: August 1, 2011Publication date: February 2, 2012Inventors: Se-young Jeong, Ho-jin Lee, Ho-geon Song, Jae-hyun Phee
-
Publication number: 20110284936Abstract: A semiconductor device and a method of fabricating a semiconductor device. The semiconductor device includes an interlayer insulation layer pattern, a metal wire pattern exposed by a passage formed by a via hole formed in the interlayer insulation layer pattern to input and output an electrical signal, and a plated layer pattern directly contacting the metal wire pattern and filling the via hole. The method includes forming an interlayer insulation layer having a metal wire pattern to input and output an electrical signal formed therein, forming a via hole to define a passage that extends through the interlayer insulation layer until at least a part of the metal wire pattern is exposed, and forming a plated layer pattern to fill the via hole and to directly contact the metal wire pattern by using the metal wire pattern exposed through the via hole as a seed metal layer.Type: ApplicationFiled: May 16, 2011Publication date: November 24, 2011Applicant: Samsung Electronics Co., LtdInventors: Ju-il CHOI, Jae-hyun Phee, Hyu-ha Lee, Ho-jin Lee, Son-kwan Hwang
-
Publication number: 20110226626Abstract: A substrate treating device may include a plating treatment portion configured to perform a plating process of a substrate, a wet treatment portion configured to perform a wet treating process of the substrate, the wet treatment portion being under the plating treatment portion, and a substrate support portion configured to support the substrate so that a plating surface of the substrate faces upward, the substrate support portion being further configured to move the substrate between the plating treatment portion and the wet treatment portion.Type: ApplicationFiled: March 3, 2011Publication date: September 22, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ju-il Choi, Uihyoung Lee, Jae-hyun Phee, Jeong-Woo Park
-
Publication number: 20100105169Abstract: A semiconductor device includes a semiconductor substrate and a via electrode. The via electrode has a first portion on the substrate and extends towards the substrate and has a plurality of spikes that extends from the first portion into the substrate, each of the spikes being spaced apart form one another.Type: ApplicationFiled: August 18, 2009Publication date: April 29, 2010Inventors: Ho-jin Lee, Hyun-soo Chung, Chang-seong Jeon, Sang-sick Park, Jae-hyun Phee
-
Publication number: 20100013094Abstract: A semiconductor package and a method of manufacturing the semiconductor package. The semiconductor package include a substrate including a plurality of pads and a plurality of bumps evenly disposed on an entire region of the substrate regardless of an arrangement of the plurality of pads. According to the present invention, a simplification of a process can be accomplished, a cost of a process can be reduced, reliability can be improved and an under-filling can become easy.Type: ApplicationFiled: July 15, 2009Publication date: January 21, 2010Applicant: Samsung Electronics Co., LtdInventors: Chajea JO, Uihyoung LEE, Jae-hyun PHEE, Jeong-Woo PARK, Ha-Young YIM