Abstract: Disclosed is a method and apparatus for encoding/decoding a video. According to an embodiment, provided is a method of setting a level for each of one or more regions, including decoding a definition syntax element related to level definition and a designation syntax element related to target designation from a bitstream; defining one or more levels based on the definition syntax element; and setting a target level designated by the designation syntax element among the defined levels for a target region designated by the designation syntax element.

Abstract: An aerosol generating device according to an aspect comprises a main body that comprises a battery and a controller, a cartridge which is coupled to the main body and comprises a liquid storage that contains liquid composition and an atomization portion that generates an aerosol by heating the liquid composition contained in the liquid storage, and a cover that forms an inner space by being coupled to the main body such that the cartridge is arranged in the inner space, wherein the main body further comprises a light source that emits light toward an inside of the liquid storage, and the cover comprises a window hole through which light entitled from the light source toward the inside of the liquid storage is transmitted to the outside of the cover.

Abstract: Disclosed are a pearlescent pigment and a preparation method therefor, wherein the pigment has a multilayered structure including a low-refractive index material layer between high-refractive index material layers on a glass flake substrate and thus has high color intensity, various colors depending on the viewing angle, and an improved sparkling effect. The pearlescent pigment according to the present invention comprises: a glass flake substrate having a D10 value of 40-80 ?m, a D50 value of 160-250 ?m, and a D90 value of 350-600 ?m and a thickness of 500 nm or more; and a metal oxide layer coated on the substrate, the metal oxide layer having a structure of a first metal oxide layer/an intermediate oxide layer containing MgO·SiO2/a second metal oxide layer.

Abstract: A memory system includes a memory device and a memory controller. The memory controller includes a core processor and a built-in self-repair (BISR) logic circuit. The core processor includes a register file with a plurality of register values corresponding to a plurality of repair commands. The BISR logic circuit receives at least one of the plurality of register values from the core processor and converts the at least one of the plurality of register values into at least one of the repair commands to output the least one of the repair commands to the memory device. The core processor transmits the at least one of the plurality of register values to the BISR logic circuit in response to a firmware instruction that is output from an external firmware coupled to the memory controller.

Abstract: A memory system includes a memory device including a plurality of banks, each including row and column spares for replacing defective rows and columns; and a memory controller suitable for controlling an operation of the memory device, wherein the memory controller includes: a built-in self-test (BIST) circuit suitable for performing a test operation on the banks and generating fail addresses for each bank based on a result of the test operation; and a built-in redundancy analysis (BIRA) circuit suitable for determining first and second spare counts by respectively counting the number of repairable row spares and repairable column spares, and selecting a target repair address from the fail addresses for each bank, according to the first and second spare counts.

Abstract: A control method of a hydraulic brake apparatus for a vehicle including a first brake device and a second brake device configured to supply hydraulic pressure to wheel brakes, and a control unit including a first controller controlling the first brake device and a second controller controlling the second brake device, includes receiving information for determining a status of the first brake device by means of the control unit; determining whether the first brake device is normally operated using the information for determining a status of the first brake by means of the control unit; and controlling at least one of the first brake device and the second brake device to decrease a hydraulic pressure loss amount in the wheel brakes when the control unit determines that the first brake is not normally operated.

Abstract: An electronic brake for a vehicle and a control method therefor according to an embodiment of the present disclosure are able to stably generate a required braking force by controlling an auxiliary brake device by an auxiliary controller, if a flow path on the auxiliary brake device that connects a main brake device and a wheel brake is unintentionally closed.

Abstract: According to at least one embodiment, the present disclosure provides a control method of an electric hydraulic brake including an auxiliary braking system generating a braking force in a vehicle when a main brake system fails, the control method comprising: determining whether the main brake system fails; opening a rear-wheel High pressure Switching Valve (HSV) connecting a rear wheel of the main brake system and a Low Pressure Accumulator (LPA) of the auxiliary braking system when the main brake system is determined to have failed; determining whether a driver intervenes in braking; and controlling the auxiliary brake system to generate a braking force in the vehicle.

Abstract: An electronic brake for a vehicle and a control method therefor according to an embodiment of the present disclosure are able to generate a braking force required to safely run the vehicle even if something is wrong with a main brake device, by controlling an auxiliary brake device, which generates a required braking force by serving as a backup for the main brake device.

Abstract: A semiconductor memory device includes a memory and a memory controller configured to control the memory. The memory controller includes a normal operation control part and a repair part. The normal operation control part is configured to control a normal operation of the memory and includes a plurality of storage spaces used while the normal operation is controlled. The repair part is configured to control a repair operation of the memory and stores faulty addresses detected while the repair operation is controlled into the plurality of storage spaces included in the normal operation control part.

Abstract: According to at least one embodiment, the present disclosure provides an electro-hydraulic brake comprising: a main brake unit configured to provide braking hydraulic pressure to a plurality of wheel cylinders by driving a motor; an auxiliary brake unit connected to the main brake unit to be filled with high-pressure braking hydraulic pressure, and configured to provide braking hydraulic pressure to the plurality of wheel cylinders when an operation error of the main brake unit occurs; a main battery configured to supply power to the main brake unit and the auxiliary brake unit; and an auxiliary battery configured to supply power to the auxiliary brake unit when the main battery fails, wherein the auxiliary brake unit comprises an auxiliary brake control unit that controls charging and discharging of the auxiliary battery, and a power module that monitors a state of the main battery and transmits the state to the auxiliary brake control unit, and a battery management module that monitors a state of charge (SO

Abstract: An electronic hydraulic brake device may include: a brake unit including a main brake unit configured to provide braking hydraulic pressure to a plurality of wheel cylinders through an operation of a motor, and an auxiliary brake unit connected to the main brake unit so as to be filled with high braking hydraulic pressure, and configured to provide braking hydraulic pressure to the plurality of wheel cylinders when an operation error of the main brake unit occurs; a first control unit configured to control the operation of the brake unit, and configured to control the auxiliary brake unit to operate when an operation error of the main brake unit occurs; and a second control unit configured to assist a part of the control of the main brake unit controlled by the first control unit and the control of the auxiliary brake unit.

Abstract: A memory system includes a memory device and a memory controller. The memory controller includes a core processor and a built-in self-repair (BISR) logic circuit. The core processor includes a register file with a plurality of register values corresponding to a plurality of repair commands. The BISR logic circuit receives at least one of the plurality of register values from the core processor and converts the at least one of the plurality of register values into at least one of the repair commands to output the least one of the repair commands to the memory device. The core processor transmits the at least one of the plurality of register values to the BISR logic circuit in response to a firmware instruction that is output from an external firmware coupled to the memory controller.

Abstract: A memory controller includes a core processor and a built-in self-repair (BISR) logic circuit. The core processor includes a register file with a plurality of register values corresponding to repair commands that control a self-repair operation of a memory device. The BISR logic circuit receives at least one of the plurality of register values from the core processor and converts the at least one of the plurality of register values into at least one of the repair commands to output the least one of the repair commands to the memory device. The core processor transmits the at least one of the plurality of register values to the BISR logic circuit in response to a firmware instruction that is output from an external firmware coupled to the memory controller.

Abstract: A memory controller includes a core processor and a built-in self-repair (BISR) logic circuit. The core processor includes a register file with a plurality of register values corresponding to repair commands that control a self-repair operation of a memory device. The BISR logic circuit receives at least one of the plurality of register values from the core processor and converts the at least one of the plurality of register values into at least one of the repair commands to output the least one of the repair commands to the memory device. The core processor transmits the at least one of the plurality of register values to the BISR logic circuit in response to a firmware instruction that is output from an external firmware coupled to the memory controller.

Abstract: A memory system includes a memory device including a plurality of banks, each including row and column spares for replacing defective rows and columns; and a memory controller suitable for controlling an operation of the memory device, wherein the memory controller includes: a built-in self-test (BIST) circuit suitable for performing a test operation on the banks and generating fail addresses for each bank based on a result of the test operation; and a built-in redundancy analysis (BIRA) circuit suitable for determining first and second spare counts by respectively counting the number of repairable row spares and repairable column spares, and selecting a target repair address from the fail addresses for each bank, according to the first and second spare counts.

Abstract: A semiconductor memory device includes a memory and a memory controller configured to control the memory. The memory controller includes a normal operation control part and a repair part. The normal operation control part is configured to control a normal operation of the memory and includes a plurality of storage spaces used while the normal operation is controlled. The repair part is configured to control a repair operation of the memory and stores faulty addresses detected while the repair operation is controlled into the plurality of storage spaces included in the normal operation control part.

Abstract: An electronic hydraulic brake device may include: a brake unit including a main brake unit configured to provide braking hydraulic pressure to a plurality of wheel cylinders through an operation of a motor, and an auxiliary brake unit connected to the main brake unit so as to be filled with high braking hydraulic pressure, and configured to provide braking hydraulic pressure to the plurality of wheel cylinders when an operation error of the main brake unit occurs; a first control unit configured to control the operation of the brake unit, and configured to control the auxiliary brake unit to operate when an operation error of the main brake unit occurs; and a second control unit configured to assist a part of the control of the main brake unit controlled by the first control unit and the control of the auxiliary brake unit.

Abstract: A method for controlling a solenoid valve current of a brake system may include: determining, by a controller, whether a difference between the pressure of a master cylinder and the pressure of a wheel cylinder is equal to or more than a preset reference value; and forming, by the controller, the pressure of the wheel cylinder by applying a sine wave pattern to an on/off control pattern while applying a current to a solenoid valve for adjusting the pressure of the wheel cylinder such that the pressure of the wheel cylinder is changed in an LMV control manner based on an upward sloping pattern, when the determination result indicates that the difference between the pressure of the master cylinder and the pressure of the wheel cylinder is equal to or more than a preset reference value.

Abstract: A method for controlling a solenoid valve current of a brake system may include: determining, by a controller, whether a difference between the pressure of a master cylinder and the pressure of a wheel cylinder is equal to or more than a preset reference value; and forming, by the controller, the pressure of the wheel cylinder by applying a sine wave pattern to an on/off control pattern while applying a current to a solenoid valve for adjusting the pressure of the wheel cylinder such that the pressure of the wheel cylinder is changed in an LMV control manner based on an upward sloping pattern, when the determination result indicates that the difference between the pressure of the master cylinder and the pressure of the wheel cylinder is equal to or more than a preset reference value.