Patents by Inventor Jae Il TAK

Jae Il TAK has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210165603
    Abstract: A method for operating a memory device includes providing a memory block including at least one source select transistor coupled between a source line and a bit line, a plurality of memory cells, and a drain select transistor, controlling a source select line coupled to the at least one source select transistor and a plurality of word lines coupled to the plurality of memory cells to be in a floating state, and applying an erase voltage to the source line and the bit line.
    Type: Application
    Filed: February 11, 2021
    Publication date: June 3, 2021
    Applicant: SK hynix Inc.
    Inventors: Byung In LEE, Hee Joung PARK, Keon Soo SHIM, Sang Heon LEE, Jae Il TAK
  • Patent number: 10950306
    Abstract: A memory device includes a memory cell array having a plurality of memory blocks sharing a source line, a peripheral circuit for performing a program operation and an erase operation on a selected memory block among the plurality of memory blocks, and a control logic for controlling the peripheral circuit. The control logic controls the peripheral circuit such that some source select transistors adjacent to the source line among a plurality of source select transistors included in an unselected memory block among the plurality of memory blocks are floated in a source line precharge operation during the program operation.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: March 16, 2021
    Assignee: SK hynix Inc.
    Inventors: Byung In Lee, Hee Joung Park, Keon Soo Shim, Sang Heon Lee, Jae Il Tak
  • Publication number: 20200211650
    Abstract: A memory device includes a memory cell array having a plurality of memory blocks sharing a source line, a peripheral circuit for performing a program operation and an erase operation on a selected memory block among the plurality of memory blocks, and a control logic for controlling the peripheral circuit. The control logic controls the peripheral circuit such that some source select transistors adjacent to the source line among a plurality of source select transistors included in an unselected memory block among the plurality of memory blocks are floated in a source line precharge operation during the program operation.
    Type: Application
    Filed: July 12, 2019
    Publication date: July 2, 2020
    Applicant: SK hynix Inc.
    Inventors: Byung In LEE, Hee Joung PARK, Keon Soo SHIM, Sang Heon LEE, Jae Il TAK
  • Patent number: 9543021
    Abstract: A semiconductor device includes a plurality of electrically coupled memory cells in a generally vertical configuration extending in a generally perpendicular direction from a semiconductor substrate, a peripheral circuit configured to program the memory cells, and a control circuit configured to program a memory cell selected from the plurality of memory cells to trap charge in the selected memory cell, and to issue at least one command to the peripheral circuit to manage a dispersion of at least a portion of the trapped charge between memory cells adjacent to the selected memory cell.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: January 10, 2017
    Assignee: SK HYNIX INC.
    Inventors: Se Jun Kim, Jae Il Tak, Kyung Hwan Park
  • Publication number: 20150262678
    Abstract: A semiconductor device includes a plurality of electrically coupled memory cells in a generally vertical configuration extending in a generally perpendicular direction from a semiconductor substrate, a peripheral circuit configured to program the memory cells, and a control circuit configured to program a memory cell selected from the plurality of memory cells to trap charge in the selected memory cell, and to issue at least one command to the peripheral circuit to manage a dispersion of at least a portion of the trapped charge between memory cells adjacent to the selected memory cell.
    Type: Application
    Filed: August 8, 2014
    Publication date: September 17, 2015
    Inventors: Se Jun KIM, Jae Il TAK, Kyung Hwan PARK