Patents by Inventor Jae In WON

Jae In WON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130292833
    Abstract: A semiconductor device may include a lower semiconductor package including at least one lower semiconductor chip, at least one upper semiconductor package mounted on the lower semiconductor package to include at least one upper semiconductor chip, a molding layer provided between the lower and upper semiconductor packages, and connection solder balls provided in the molding layer to electrically connect the lower and upper semiconductor packages to each other. Each of the connection solder balls may include a portion protruding upward from the molding layer, and there may be no gap between the connection solder balls and the molding layer.
    Type: Application
    Filed: March 15, 2013
    Publication date: November 7, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae In WON, KYHYUN JUNG, JaeYong PARK