Abstract: A data output buffer circuit for a semiconductor device for transferring read cell data to the peripheral circuits, comprising an input terminal for inputting the read cell data, a first NMOS transistor for transferring the data from the input terminal when it has a first logic level, a first PMOS transistor for transferring the data from the input terminal when it has a second logic level, a second PMOS transistor for transferring a high logic signal in response to an output signal from the first NMOS transistor, a second NMOS transistor for transferring a low logic signal in response to an output signal from the first PMOS transistor, and an output terminal for outputting the high logic signal from the second PMOS transistor or the low logic signal from the second NMOS transistor to the peripheral circuits.

Abstract: A signal transfer circuit for a synchronous memory device, comprising an input terminal for inputting a clock signal, an internal address generator for generating an internal address signal, a multiplexing circuit for selectively transferring an external address signal and the internal address signal from the internal address generator, a multiplexing controller for controlling the operation of the multiplexing circuit in response to the clock signal from the input terminal, an internal circuit for generating a data signal in response to the external or internal address signal transferred by the multiplexing circuit, a data output buffer for buffering the data signal generated by the internal circuit and outputting the buffered data signal externally, an output buffer controller for controlling the operation of the data output buffer in response to the clock signal from the input terminal, a switching circuit connected between the internal circuit and the data output buffer, for performing a switching operati

Abstract: A data signal distribution circuit for a synchronous memory device comprising a data generation source for generating successive data signals in response to an external clock signal. The data signal distribution circuit comprises at least two control switches for switching the data signals from the data generation source to at least two peripheral circuits, a strobe signal generator for delaying the external clock signal by a propagation delay time of the data generation source and generating a strobe signal in response to the delayed external clock signal, and an internal address generator for generating an internal address signal in response to the strobe signal from the strobe signal generator and supplying the generated internal address signal to the control switches. The strobe signal has a predetermined logic level for a predetermined duration beginning with a pulse edge of the delayed external clock signal.