Abstract: An image sensing device providing improved image quality includes a pixel array that outputs a pixel signal, a comparator that outputs a comparison result signal by comparing a reference signal and the pixel signal, a counter that outputs a count result signal having m bits by counting the comparison result signal, and an image signal processor that outputs an image signal having n bits by correcting the count result signal, wherein m and n are integers, and m is greater than n.

Abstract: An image sensor includes a pixel array and a readout circuit. The pixel array includes a first unit pixel region including first, second and third sub-pixel regions having a first color filter, sequentially disposed along a first row line, and sharing a first floating diffusion region, and a second unit pixel region including a first, second and third sub-pixel regions having a second color filter, sequentially disposed along a second row line, and sharing a second floating diffusion region.

Abstract: An electronic device includes a pixel array that outputs a raw image including color pixels and specific pixels, a logic circuit that outputs a first binned image by performing first binning on pixels in a row direction for each unit kernel of the raw image, and a processor that outputs a second binned image by performing second binning on the first binned image. When a unit kernel includes at least one of the specific pixels, a column to which the at least one specific pixel belongs is read out at a readout timing different from a readout timing of a column to which none of the specific pixels belong and undergoes the first binning. The second binning combines a third binned image of the column to which none of the specific pixels belong with a fourth binned image of the column to which the at least one specific pixel belongs.

Abstract: An image sensing device providing improved image quality includes a pixel array that outputs a pixel signal, a comparator that outputs a comparison result signal by comparing a reference signal and the pixel signal, a counter that outputs a count result signal having m bits by counting the comparison result signal, and an image signal processor that outputs an image signal having n bits by correcting the count result signal, wherein m and n are integers, and m is greater than n.

Abstract: An image sensor includes a pixel array and a readout circuit. The pixel array includes a first unit pixel region including first, second and third sub-pixel regions having a first color filter, sequentially disposed along a first row line, and sharing a first floating diffusion region, and a second unit pixel region including a first, second and third sub-pixel regions having a second color filter, sequentially disposed along a second row line, and sharing a second floating diffusion region.

Abstract: An electronic device includes a pixel array that outputs a raw image including color pixels and specific pixels, a logic circuit that outputs a first binned image by performing first binning on pixels in a row direction for each unit kernel of the raw image, and a processor that outputs a second binned image by performing second binning on the first binned image. When a unit kernel includes at least one of the specific pixels, a column to which the at least one specific pixel belongs is read out at a readout timing different from a readout timing of a column to which none of the specific pixels belong and undergoes the first binning. The second binning combines a third binned image of the column to which none of the specific pixels belong with a fourth binned image of the column to which the at least one specific pixel belongs.

Abstract: An image sensor is provided. The image sensor includes a pixel configured to generate a reset signal and an image signal, a comparator configured to compare the reset signal with a reference signal and generate a first comparison signal, a counter configured to generate a first count value corresponding to the reset signal based on a clock signal and the first comparison signal, and a reference signal generator configured to generate the reference signal which changes between a first level corresponding to a maximum reset count value of the counter and a second level corresponding to a minimum reset count value of the counter during a reset signal period.

Abstract: An image sensor is provided. The image sensor includes a pixel configured to generate a reset signal and an image signal, a comparator configured to compare the reset signal with a reference signal and generate a first comparison signal, a counter configured to generate a first count value corresponding to the reset signal based on a clock signal and the first comparison signal, and a reference signal generator configured to generate the reference signal which changes between a first level corresponding to a maximum reset count value of the counter and a second level corresponding to a minimum reset count value of the counter during a reset signal period.

Abstract: An image sensor is provided. The image sensor includes a pixel configured to generate a reset signal and an image signal, a comparator configured to compare the reset signal with a reference signal and generate a first comparison signal, a counter configured to generate a first count value corresponding to the reset signal based on a clock signal and the first comparison signal, and a reference signal generator configured to generate the reference signal which changes between a first level corresponding to a maximum reset count value of the counter and a second level corresponding to a minimum reset count value of the counter during a reset signal period.

Abstract: An image sensor includes a pixel array including a plurality of pixels, a row driver configured to control an operation of each of the plurality of pixels, a voltage supply line connected to a reset transistor included in each of the plurality of pixels, and a voltage supply circuit which detects a signal from the voltage supply line and supplies one of a first voltage and a second voltage to the voltage supply line based on the signal from the voltage supply line.

Abstract: An image sensor includes a first column pair and a second column pair among a plurality of columns of a pixel array, an analog-to-digital converter pair, and a switch arrangement circuit configured to connect the first column pair with the analog-to-digital converter pair in response to first switch control signals such that two rows among a plurality of rows in the pixel array are read during a single access time.

Abstract: An image sensor includes a pixel array including at least one active pixel and at least one line-optical black (L-OB) pixel arranged in a matrix including first to nth rows and first to mth columns, the pixel array configured to output a pixel signal and a dark-level offset signal in units of columns during a read-out operation in one of the first to nth rows; a row driver configured to output a selection control signal to the first to nth rows; and an analog-to-digital converter (ADC) block configured to digitize the pixel signal and the dark-level offset signal. In the pixel array, a dark-level offset signal is simultaneously output from an L-OB pixel in another row during the read-out operation in one of the first to nth rows. Here, ‘n’ and ‘m’ each denote an integer that is equal to or greater than ‘2’.

Abstract: An image sensor is provided. The image sensor includes a pixel configured to generate a reset signal and an image signal, a comparator configured to compare the reset signal with a reference signal and generate a first comparison signal, a counter configured to generate a first count value corresponding to the reset signal based on a clock signal and the first comparison signal, and a reference signal generator configured to generate the reference signal which changes between a first level corresponding to a maximum reset count value of the counter and a second level corresponding to a minimum reset count value of the counter during a reset signal period.

Abstract: An image sensor includes a pixel array including a plurality of pixels, a row driver configured to control an operation of each of the plurality of pixels, a voltage supply line connected to a reset transistor included in each of the plurality of pixels, and a voltage supply circuit which detects a signal from the voltage supply line and supplies one of a first voltage and a second voltage to the voltage supply line based on the signal from the voltage supply line.

Abstract: An image sensor includes a pixel array including at least one active pixel and at least one line-optical black (L-OB) pixel arranged in a matrix including first to nth rows and first to mth columns, the pixel array configured to output a pixel signal and a dark-level offset signal in units of columns during a read-out operation in one of the first to nth rows; a row driver configured to output a selection control signal to the first to nth rows; and an analog-to-digital converter (ADC) block configured to digitize the pixel signal and the dark-level offset signal. In the pixel array, a dark-level offset signal is simultaneously output from an L-OB pixel in another row during the read-out operation in one of the first to nth rows. Here, ‘n’ and ‘m’ each denote an integer that is equal to or greater than ‘2’.

Abstract: An image sensor includes a first column pair and a second column pair among a plurality of columns of a pixel array, an analog-to-digital converter pair, and a switch arrangement circuit configured to connect the first column pair with the analog-to-digital converter pair in response to first switch control signals such that two rows among a plurality of rows in the pixel array are read during a single access time.

Abstract: A sub pixel includes a photodetector and a column line output circuit. The photodetector is configured to output an electrical signal based on a detected amount of photons. The column line output circuit is configured to generate an output signal based on the electrical signal. The output signal is one of a current from a current source and a comparison signal indicative of binary output data.