Patents by Inventor Jae Jin Kwon

Jae Jin Kwon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11664297
    Abstract: Provided is a method of manufacturing a semiconductor package, the method including a first step for forming a primary solder ball on an under bump metallurgy (UBM) structure, and a second step for forming a secondary solder ball on an upper surface of the UBM structure by performing a reflow process on the primary solder ball while a side wall of the UBM structure is exposed.
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: May 30, 2023
    Assignee: LBSEMICON CO., LTD.
    Inventor: Jae Jin Kwon
  • Publication number: 20210366809
    Abstract: Provided is a method of manufacturing a semiconductor package, the method including a first step for forming a primary solder ball on an under bump metallurgy (UBM) structure, and a second step for forming a secondary solder ball on an upper surface of the UBM structure by performing a reflow process on the primary solder ball while a side wall of the UBM structure is exposed.
    Type: Application
    Filed: August 10, 2021
    Publication date: November 25, 2021
    Inventor: Jae Jin KWON
  • Patent number: 11127658
    Abstract: Provided is a method of manufacturing a semiconductor package, the method including a first step for forming a primary solder ball on an under bump metallurgy (UBM) structure, and a second step for forming a secondary solder ball on an upper surface of the UBM structure by performing a reflow process on the primary solder ball while a side wall of the UBM structure is exposed.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: September 21, 2021
    Assignee: LBSEMICON CO., LTD.
    Inventor: Jae Jin Kwon
  • Patent number: 10825788
    Abstract: Provided is a method of manufacturing compliant bumps, the method including preparing an electronic device including at least one conductive pad, forming an elastic resin layer on the electronic device, forming a photoresist layer on the elastic resin layer, forming a first photoresist pattern on a region spaced apart from a region where the conductive pad is located, forming a second photoresist pattern having a lower cross-sectional area greater than an upper cross-sectional area, forming an elastic resin pattern having a lower cross-sectional area greater than an upper cross-sectional area, on a region spaced apart from a region where the conductive pad is located, and forming a conductive wiring pattern covering at least a part of the elastic resin pattern and extending to the conductive pad.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: November 3, 2020
    Assignee: LBSEMICON CO., LTD.
    Inventor: Jae Jin Kwon
  • Publication number: 20200266164
    Abstract: Provided is a method of manufacturing compliant bumps, the method including preparing an electronic device including at least one conductive pad, forming an elastic resin layer on the electronic device, forming a photoresist layer on the elastic resin layer, forming a first photoresist pattern on a region spaced apart from a region where the conductive pad is located, forming a second photoresist pattern having a lower cross-sectional area greater than an upper cross-sectional area, forming an elastic resin pattern having a lower cross-sectional area greater than an upper cross-sectional area, on a region spaced apart from a region where the conductive pad is located, and forming a conductive wiring pattern covering at least a part of the elastic resin pattern and extending to the conductive pad.
    Type: Application
    Filed: December 28, 2017
    Publication date: August 20, 2020
    Inventor: Jae Jin KWON
  • Publication number: 20200168506
    Abstract: Disclosed is a method of fabricating a semiconductor package, the method including sawing a portion of the thickness of a substrate downward from an upper surface of the substrate along a boundary region between individual chips to form a sawing groove; forming a resin material on the sawing groove and the substrate; removing portions of the resin material to form post spaces on the substrate; filling a conductive material into the post spaces to form posts; respectively forming redistribution layers on the posts; respectively forming insulating film patterns or under bump metal (UBM) patterns on the redistribution layers; respectively bonding solder balls onto the redistribution layers or the UBM patterns; and sawing the resin material to separate into individual chips.
    Type: Application
    Filed: November 24, 2019
    Publication date: May 28, 2020
    Applicant: Lbsemicon Inc.
    Inventors: Jae Jin Kwon, Jin Kuk Lee
  • Publication number: 20200168477
    Abstract: Disclosed is a method of fabricating a semiconductor package, the method including forming a first resin material, in which alignment grooves are formed, on a carrier substrate; respectively aligning semiconductor chips, to which posts are respectively attached, in the alignment grooves; forming a second resin material on the carrier substrate, the semiconductor chips, and the posts; grinding a portion of the second resin material such that portions of the posts are exposed; respectively forming redistribution layers on the exposed posts; respectively forming insulating film patterns or UBM patterns on the redistribution layers; respectively bonding solder balls onto the redistribution layers or the UBM patterns; removing the carrier substrate from the first resin material and the semiconductor chips; and sawing the first resin material and the second resin material to separate into individual chips.
    Type: Application
    Filed: November 24, 2019
    Publication date: May 28, 2020
    Applicant: Lbsemicon Inc.
    Inventors: Jae Jin Kwon, Jin Kuk Lee
  • Publication number: 20190237392
    Abstract: Provided is a method of manufacturing a semiconductor package, the method including a first step for forming a primary solder ball on an under bump metallurgy (UBM) structure, and a second step for forming a secondary solder ball on an upper surface of the UBM structure by performing a reflow process on the primary solder ball while a side wall of the UBM structure is exposed.
    Type: Application
    Filed: May 11, 2017
    Publication date: August 1, 2019
    Applicant: LBSEMICON CO., LTD.
    Inventor: Jae Jin KWON