Patents by Inventor Jae Joon AHN

Jae Joon AHN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9397757
    Abstract: A semiconductor package includes a package substrate, a first semiconductor substrate and a second semiconductor substrate stacked on the package substrate, and an optical transceiver that generates and receives an optical signal travelling between the package substrate and the second semiconductor substrate using an infrared (IR) ray that passes through the first semiconductor substrate.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: July 19, 2016
    Assignee: SK HYNIX INC.
    Inventors: In Chul Hwang, Il Hwan Cho, Ki Young Kim, Kyoung Mo Yang, Jae Joon Ahn, Chong Ho Cho
  • Publication number: 20150222364
    Abstract: A semiconductor package includes a package substrate, a first semiconductor substrate and a second semiconductor substrate stacked on the package substrate, and an optical transceiver that generates and receives an optical signal travelling between the package substrate and the second semiconductor substrate using an infrared (IR) ray that passes through the first semiconductor substrate.
    Type: Application
    Filed: June 27, 2014
    Publication date: August 6, 2015
    Inventors: In Chul HWANG, Il Hwan CHO, Ki Young KIM, Kyoung Mo YANG, Jae Joon AHN, Chong Ho CHO
  • Patent number: 8624375
    Abstract: A semiconductor package includes: first, second, third and fourth semiconductor chips stacked while having the arrangement of chip selection vias; and a connection unit provided between a second semiconductor chip and a third semiconductor chip, and configured to mutually connect some of the chip selection vias of the second and third semiconductor chips and disconnect the others of the chip selection vias of the second and third semiconductor chips, wherein the first and second semiconductor chips and the third and fourth semiconductor chips are stacked in a flip chip type.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: January 7, 2014
    Assignee: SK Hynix Inc.
    Inventors: Bok Gyu Min, Joon Ki Hong, Tae Hoon Kim, Da Un Nah, Jae Joon Ahn, Ki Bum Kim
  • Publication number: 20120032342
    Abstract: A semiconductor package includes: first, second, third and fourth semiconductor chips stacked while having the arrangement of chip selection vias; and a connection unit provided between a second semiconductor chip and a third semiconductor chip, and configured to mutually connect some of the chip selection vias of the second and third semiconductor chips and disconnect the others of the chip selection vias of the second and third semiconductor chips, wherein the first and second semiconductor chips and the third and fourth semiconductor chips are stacked in a flip chip type.
    Type: Application
    Filed: December 29, 2010
    Publication date: February 9, 2012
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Bok Gyu MIN, Joon Ki HONG, Tae Hoon KIM, Da Un NAH, Jae Joon AHN, Ki Bum KIM