Abstract: An electronic device includes a semiconductor memory. A method for fabricating the electronic device includes forming a first memory cell extending vertically from a surface of substrate and having a first upper portion that protrudes laterally, forming a second memory cell extending vertically from the surface of the substrate and having a second upper portion that protrudes laterally towards the first upper portion, and forming a liner layer over the first and second memory cells, the liner layer having a first portion disposed over the first upper portion and a second portion disposed over the second upper portion, the first and second portions of the liner layer contacting each other.

Abstract: A memory device, a host device and a memory system are provided. The memory device may include a plurality of storage units configured to store data, and at least one device controller configured to, receive a read command from at least one host device and to read data stored in the plurality of storage units in response to the read command, the at least one host device including at least one host memory including a plurality of HPB (high performance boosting) entry storage regions, and provide the at least one host device with a response command, the response command indicating an activation or deactivation of the plurality of HPB entry storage regions, the response command including HPB entry type information which indicates a HPB entry type of the HPB entry storage region.

Abstract: An apparatus for embedding a sentence feature vector according to an embodiment includes a sentence acquisitor configured to acquire a first sentence and a second sentence, each including one or more words; a vector extractor configured to extract a first feature vector corresponding to the first sentence and a second feature vector corresponding to the second sentence by independently inputting each of the first sentence and the second sentence into a feature extraction network; and a vector compressor configured to compress the first feature vector and the second feature vector into a first compressed vector and a second compressed vector, respectively, by independently inputting each of the first feature vector and the second feature vector into a convolutional neural network (CNN)-based vector compression network.

Abstract: An image sensing device is provided to include a pixel array having a plurality of pixels arranged in a matrix shape. Each of the pixels includes: a control node configured to generate a hole current in a substrate; a detection node configured to capture photocharge migrated by the hole current, formed in a shape whose at least part is partially open, and disposed to surround the control node, and a low resistance region including a dielectric layer formed in the substrate, and disposed in the opening on of the detection node. The low resistance region includes an inner low resistance region disposed between the control node and the center of the pixel.

Abstract: An optical sensor includes a substrate, a photoelectric element disposed on the substrate and that includes a first electrode, an intermediate layer disposed on the first electrode, and a second electrode disposed on the intermediate layer, a barrier layer disposed on the second electrode, an insulating layer that covers the photoelectric element and the barrier layer, and a bias electrode disposed on the insulating layer and electrically connected to the second electrode. The barrier layer is spaced apart from the first electrode.

Abstract: A method for regenerating silicon from silicon waste includes: placing and mixing silicon waste, a solvent having pH of approximately 5 to approximately 6, and a surfactant within a container; and injecting air into the container to separate floating matters and precipitates. Accordingly, since silicon is easily separated from the silicon waste, the regeneration yield of silicon is increased. Since the regenerated silicon is recyclable, it may be possible to obtain important substitution effect of high-purity silicon the entire amount of which depends on import. Moreover, environmental pollution may be reduced because the amount of the silicon waste disposed of by burial is decreased.

Abstract: A wafer level LED interposer and its manufacturing method is provided. The wafer level LED interposer includes: a LED chip of which N-type electrode and p-type electrode are formed on the upper side; an interposer substrate formed with through vias at each position corresponding to the N-type electrode and the p-type electrode and bonded to the upper side of the LED chip, wherein the N-type electrode and p-type electrode are connected to each through via; a redistribution layer formed on the upper surface of the interposer substrate and electrically connected to the through vias; a solder resist layer coated on the upper surface of the interposer substrate for a part of the redistribution layer selectively to be opened; and an external connector formed at the position where the redistribution layer is opened.

Abstract: A method for regenerating silicon from silicon waste includes: placing and mixing silicon waste, a solvent having pH of approximately 5 to approximately 6, and a surfactant within a container; and injecting air into the container to separate floating matters and precipitates. Accordingly, since silicon is easily separated from the silicon waste, the regeneration yield of silicon is increased. Since the regenerated silicon is recyclable, it may be possible to obtain important substitution effect of high-purity silicon the entire amount of which depends on import. Moreover, environmental pollution may be reduced because the amount of the silicon waste disposed of by burial is decreased.

Abstract: A packaged integrated circuit device is disclosed, in which there are provided at least one pad formed at an active surface and a conductive line which is connected with a non-active surface along a lateral surface, so that a connection between the pad and the non-active surface is performed through a redistribution substrate. In the packaged integrated circuit device, an assembling work using a whole semiconductor substrate and productivity are enhanced. A foreign substance is prevented from being inputted into a sensor part formed on an active surface of a semiconductor substrate, and a small size package product can be possible. It is well applicable to the semiconductor products, which are designed to operate in accordance with external physical signals.

Abstract: The present invention provides a method for manufacturing a wafer level chip scale package using a redistribution substrate, which has patterned bump pairs connected by redistribution lines and formed on a transparent insulating substrate. The redistribution substrate is produced separately from a wafer and then bonded to the wafer. One part of each bump pair is in contact with a chip pad on the active surface of the wafer, and the other part coincides with one of holes formed in the wafer. Conductive lines are formed in the holes and on the non-active surface of the wafer. External connection terminals are formed on the conductive lines at the non-active surface.

Abstract: The present invention provides a method for manufacturing a wafer level chip scale package using a redistribution substrate, which has patterned bump pairs connected by redistribution lines and formed on a transparent insulating substrate. The redistribution substrate is produced separately from a wafer and then bonded to the wafer. One part of each bump pair is in contact with a chip pad on the active surface of the wafer, and the other part coincides with one of holes formed in the wafer. Conductive lines are formed in the holes and on the non-active surface of the wafer. External connection terminals are formed on the conductive lines at the non-active surface.

Abstract: The invention provides a method insuring that each read channel optimization step is controllable in terms of quality divergence, that a systematic response can be made which can be readily automated. The method is applicable to a pre-existing read channel optimization (RCO) script. The method includes the following operations. Acquiring a first quality measure and a first parameter list. Performing the pre-existing RCO script creating a second quality measure and a second parameter list based upon the first parameter list. Convergence processing the first and second quality measures and parameter lists.

Abstract: Methods and apparatus are disclosed determining the presence of base line popping noise for a read head inside an assembled disk drive, as well as, determining read bias conditions for operating the read head free of base line popping noise. These further include performance evaluation of the read head for read bias conditions free of base line popping noise. They also include repairing the read head using DC write current and read bias current within the assembled disk drive.

Abstract: The invention provides a method insuring that each read channel optimization step is controllable in terms of quality divergence, that a systematic response can be made which can be readily automated. The method is applicable to a pre-existing read channel optimization (RCO) script. The method includes the following operations. Acquiring a first quality measure and a first parameter list. Performing the pre-existing RCO script creating a second quality measure and a second parameter list based upon the first parameter list. Convergence processing the first and second quality measures and parameter lists.

Abstract: The invention includes methods determining the presence of base line popping noise for a read head inside an assembled disk drive, as well as, determining read bias conditions for operating the read head free of base line popping noise. The invention further includes performance evaluation of the read head for read bias conditions free of base line popping noise. The invention also includes repairing the read head using DC write current and read bias current within the assembled disk drive.

Abstract: An automated apparatus for three dimensional stack package devices provides mass production of J-lead type stack packages. The apparatus includes a package loader and a package loader/unloader for loading upper and lower individual packages and for unloading packages which have been stacked and soldered; an indexing system for receiving and aligning the upper and lower individual packages and for transporting the stacked upper and lower packages, an applying unit for applying a solder flux or a solder paste to metal leads of the upper individual packages, first and second transfer tools for transferring the individual packages to the applying unit and to the indexing system; and a heating unit for heating the stacked upper and lower packages so that metal leads of the upper and lower packages are solder jointed.

Abstract: A package for a semiconductor chip including a plurality of input/output pads includes an insulating layer and a plurality of conductive traces. The insulating layer has a first surface for bonding with the surface of the semiconductor chip so that the input/output pads are exposed adjacent the insulating layer. The conductive traces are provided on a second surface of the insulating layer opposite the first surface wherein each of the conductive traces corresponds to a respective one of the input/output pads. In particular, the conductive traces are adapted to receive a plurality of bonding wires each of which corresponds to a respective one of the input/output pads. Accordingly, each of the bonding wires can be bonded at a first end to the respective input/output pad and at a second end to the respective conductive trace.

Abstract: A stacking and soldering apparatus for a three dimensional stack package devices includes a first base plate for receiving the first individual package devices to be stacked and having a heater for heating metal lead portions of the first individual package devices and; a second base plate for receiving the second individual package devices to be stacked and having a heater for heating metal lead portions of the second individual package devices. A package loader is used for transferring the individual packages to the first and the second base plates; and a transferring device is used for transferring the first individual package devices in the first base plate to the second base plate.

Abstract: A magnetic disk drive apparatus adopting a PRML (Partial Response Maximum Likelihood) optimizes a Viterbi detector threshold value in order to optimize a read channel. The apparatus includes the steps of setting an average range of Viterbi detector threshold values for each head and storing the average range. The apparatus additionally includes the steps of writing and reading test data by using Viterbi detector threshold values within the average range of the Viterbi detector threshold values with respect to corresponding zones of the head, so as to evaluate minimum error rates for the respective zones of the head; setting the Viterbi detector threshold values corresponding to the minimum error rates for the respective zones of the head, as optimal Viterbi detector threshold values of the corresponding zones, and storing the optimal Viterbi detector threshold values into a storage; and storing the optimal Viterbi detector threshold values into a maintenance area of a disk.

Abstract: An overvoltage and surge protection circuit for a hard disk drive is provided. The overvoltage and surge protection circuit is intended for protecting an interior circuit part from a surge voltage caused by an overvoltage generated due to wrong insertion of first and second power supply voltages, and an external condition, in a hard disk drive which receive the first power supply voltage as an operational voltage of an interior circuit device and the second power supply voltage as a device driving voltage. The overvoltage and surge protection circuit includes an overvoltage protection circuit having a first and second power supply input terminals for receiving the first and second power supply voltages, respectively, and a surge protection circuit.