Abstract: Aspects of the present disclosure include a wafer level chip package and method of manufacture. The wafer level chip package includes one or more semiconductor dies. A stiffener wall surrounds the one or more semiconductor dies. The stiffener wall extends from an active side to an inactive side of the semiconductor dies. There is a compliant layer encasing the one or more semiconductor dies and the stiffener wall. There is a redistribution layer disposed on the active side of the one or more semiconductor dies. The redistribution layer includes a plurality of interconnects extending to a plurality of ball pads on a surface of the redistribution layer. A plurality of solder balls is electrically connected to the plurality of ball pads.