Abstract: An optical imaging device which receives an optical collimated input beam, the device having a pair of axicon lenses through which a beam is directed to generate a collimated ring beam, wherein the ring beam is scattered from a substance to generate a return beam, and to bypass a reflector that redirects the return beam to prevent the return beam from interfering with the input beam; and a detector which detects an image projected by the return beam.

Abstract: An optical imaging device which receives an optical collimated input beam, the device having a pair of axicon lenses through which a beam is directed to generate a collimated ring beam, wherein the ring beam is scattered from a substance to generate a return beam, and to bypass a reflector that redirects the return beam to prevent the return beam from interfering with the input beam; and a detector which detects an image projected by the return beam.

Abstract: This document describes a general system for noise reduction, as well as a specific system for Magnetic Resonance Imaging (MRI) and Nuclear Quadrupole Resonance (NQR). The general system, which is called Calculated Readout by Spectral Parallelism (CRISP), involves reconstruction and recombination of frequency-limited broadband data using separate narrowband data channels to create images or signal profiles. A multi-channel CRISP system can perform this separation using (1) frequency tuned hardware, (2) a frequency filter-bank (or equivalent), or (3) a combination of implementations (1) and (2). This system significantly reduces what we call cross-frequency noise, thereby increasing signal-to-noise-ratio (SNR). A multi-channel CRISP system applicable to MRI and NQR are described.

Abstract: This document describes a general system for noise reduction, as well as a specific system for Magnetic Resonance Imaging (MRI) and Nuclear Quadrupole Resonance (NQR). The general system, which is called Calculated Readout by Spectral Parallelism (CRISP), involves reconstruction and recombination of frequency-limited broadband data using separate narrowband data channels to create images or signal profiles. A multi-channel CRISP system can perform this separation using (1) frequency tuned hardware, (2) a frequency filter-bank (or equivalent), or (3) a combination of implementations (1) and (2). This system significantly reduces what we call cross-frequency noise, thereby increasing signal-to-noise-ratio (SNR). A multi-channel CRISP system applicable to MRI and NQR are described.

Abstract: An MRI method is provided for determining the arrival of selected contrast material at a target artery or other fluid-carrying vessel after injection of contrast material at a remote vascular site. By precisely knowing the arrival time, an additional MR angiography scan of the artery may be readily coordinated with the onset of artery enhancement. Initiation of this MR angiography scan may be immediate. Alternatively, determination of the arrival time of a test bolus of contrast to the imaging site can be used to calculate the transit time of a test bolus from the injection site to the imaging site. This information may then be used as an estimate of a subsequent MR angiography scan using a full bolus of contrast. The method for determining contrast arrival includes injecting the contrast material at an injection site, and simultaneously commencing acquisition of a succession of MR images of a section taken through the target vessel, proximate to the imaging site.

Abstract: A semiconductor device with a trench element isolation structure having a trench element isolation film formed to have a small width at the boundary between an active region and a field region, thereby capable of obtaining an improved element isolation function while easily planarizing an insulating film formed in the trench. A thick oxide film is formed at the field region provided with no trench, thereby preventing formation of a parasitic capacitor between the semiconductor substrate and the gate electrode.

Abstract: A method for the fabrication of a semiconductor device, capable of reducing the step between the cell region and the peripheral circuit region by forming a storage electrode having a similar height to that of a bit line in a region devoid of the bit line, and of establishing a cylindrical storage electrode without using an additional storage electrode mask by making an etch barrier layer over the bit line serve as a self-aligned etch barrier when a storage electrode contact hole is formed by an etch process using a storage electrode contact hole mask. It can ensure a sufficient allowance of depth of focus for subsequent lithography processes in addition to being simple and improving reliability.

Abstract: There are disclosed a semiconductor device and a method for fabrication thereof. The semiconductor device comprises an insulating film for well isolation which electrically insulates N-well from P-well, the drain electrode of PMOS and the drain electrode of NMOS being adjacent to the trench for well isolation, and a conductive wire filling one contact hole which interconnects the drain electrodes of N-well with those of P-well. The semiconductor device is very reduced in size, and thus, high integration thereof can be achieved.

Abstract: A semiconductor device having a structure capable of obtaining an increased alignment margin for a mask without any increase in the area of the semiconductor device by forming a contact plug on a drain while forming a contact pad on a source without forming contact plugs on both the source and the drain in a simultaneous manner, and a method for fabricating the semiconductor device. The contact pad has an upper portion partially overlapping with a portion of an insulating film surrounding a contact hole in which the contact pad is buried. Accordingly, it is possible to easily carry out the contact process.

Abstract: A method of manufacturing a semiconductor device. A conductive layer for the prevention of the capacitor coupling phenomenon is formed between a gate electrode and a bit line. A desired voltage is applied to the conductive layer. The capacitor coupling phenomenon between the bit line and the word line is eliminated as a result. Also, the contact size is reduced by forming a bit line contact with a self alignment method using the conductive layer and by forming a charge storage electrode contact with a self alignment method using the bit line and the conductive layer.

Abstract: There is disclosed a semiconductor device remarkably reduced in the area of the element isolation region and in the area of the substrate electrode, thereby contributing to high integration, which comprises a P type semiconductor substrate containing an N well and a P well and a trench element isolation film therein, the trench element isolation film being between the N well and P well, a P-MOSFET and an N-MOSFET established in each N well and P well, respectively, and an N type substrate electrode which is formed in contact with the source electrode of the P-MOSFET and is applied by V.sub.DD voltage.

Abstract: The semiconductor connecting device comprises a first conductive layer to be connected electrically; an insulating film covering the first conductive layer in such a way as to expose a predetermined portion of the first conductive layer, resulting in forming a contact hole; a conductive material pad formed in the contact hole so as to be connected with the first conductive layer, in a limited way over the upper surface of the insulating film; a second conductive layer formed on the extended conductive material pad, being connected with the first conductive layer; an etching barrier material formed on said conductive material pad of said contact hole and a part of the extending region, said second conductive layer being formed on the region both of said conductive material pad which is not covered with said etching barrier material and which is covered by said etching barrier material.

Abstract: A contact of a semiconductor device has an interlayer-insulating film sandwiched between upper and lower conductive line patterns, a conductive pad for electrically connecting the upper and lower conductive line patterns via a contact hole formed in the interlayer-insulating film to expose the lower conductive line pattern to the upper conductive line pattern, and a barrier material pattern formed on the upper conductive line pattern and conductive pad to partially overlap the conductive pad with the upper conductive line pattern, so that the lower and upper conductive line patterns on both sides of the interlayer-insulating film partially overlap with each other without damaging the lower conductive line pattern, thereby improving packing density of the semiconductor device. Also, a manufacturing method of the contact is provided.

Abstract: The semiconductor device comprising a P type semiconductor substrate, first and second P-wells, an N-well between the first and the second P-wells, trench element-isolating films for electrically separating the wells from each other and the first P-well from the P type semiconductor substrate, and an N type buried region formed below a first P-well between the trench element-isolating films, which is suitable to high integration and improved in operating speed.

Abstract: The semiconductor connecting device is comprised of a device separation insulating film, a source region and a drain region formed at predetermined portions of a semiconductor substrate; an interlayer insulating film formed on the device separation insulating film and on the drain region, having a contact hole through which a portion of the device separation film is exposed along with a portion of the drain region; a conductive plug formed on the exposed portion of the drain region and on the exposed portion of the drain region within the contact hole, the drain region-sided conductive plug being thinner than the device separation insulating film-sided one; and bit lines formed on the conductive material plug and the interlayer insulating film, coming into contact with them, respectively. The bit line connected with the drain region scarcely overlaps the source region where the charge storage electrode is formed, bringing about a reduction of needed area resulting in a highly integrated semiconductor device.

Abstract: A method comprising the steps of forming an insulating film on a semiconductor substrate in which a certain infrastructure is built, forming a series of conductive wirings on the insulating film, forming a blanket interlayer insulating film over the resulting structure, forming first photoresist film patterns on the interlayer insulating film, the side walls of said patterns each being located above the conductive wirings, forming sacrificial film spacers at the side walls of the first photoresist film patterns, forming second photoresist film patterns on the interlayer insulating film between the sacrificial film spacers, and forming contact holes to expose areas of the conductive wirings by sequentially removing the sacrificial spacers and the thus exposed areas of the interlayer insulating film, which results in an improvement in the operating reliability of semiconductor devices and the production yield as well as the high integration of devices.

Abstract: A method for making of a charge storage electrode in a semiconductor device is disclosed.The method comprises the steps of forming a first silicon film into a second protruded silicon film which is aslant at its both sides, forming a first thin insulating film over the second silicon film, and applying an anisotropic dry etching to the first insulating film and the second silicon film to form a vertical structure of a third silicon film, said anisotropic dry etching allowing the upper first insulating film to be removed prior to the side first insulating film, which subsequently remains in a thinner thickness to act as an obstacle to the anisotropic dry etching for the side portions of the protruded second silicon film, so that the central portion of the protruded second silicon film is etched in a larger quantity than the side portions.

Abstract: The present invention provides a method for manufacturing a capacitor in a semiconductor device which increases a capacitance of the memory cell and improves a step coverage of a conducting material. The present invention provides a method for manufacturing a capacitor in a semiconductor device, comprising steps of: forming a first conducting layer 2, an oxide layer 3 and an A--B alloy 4a on an insulation layer 1 sequentially; settling a superfluous B material 4c dissolved in a A material 4b on the oxide layer 3 by a heat treatment so that the B material is separated from the A material; only etching the A material 4b by an echant and etching an exposed oxide layer 3 by using a settled B material 4c as an etch barrier; and etching an exposed first conducting layer 2 up to an intended depth by using the separated B material 4c and a residual oxide layer 3 as an etch barrier.

Abstract: A method of making a self-aligned contact in a semiconductor device has some advantages in that the increasing tolerance of contact mask for following the contact hole may lead to reduction of the contact area by the following means: at the side wall of contact hole which connects the first conductive line and the third line up and down, a silicon spacer which insulates from the second conductive line is formed; then, the said spacer in part or whole is thermally oxidized and the upper part of silicon spacer is insulated, thus forming the contact hole thereof.

Abstract: A semiconductor connection device capable of reducing the area of connection portions by minimizing an overlapping area between a lower first conduction line and an upper second conduction line at a contact region defined in the first conduction line upon connecting the second conduction line to the first conduction line. The minimized overlapping area can be obtained by forming the second conduction line in a self-aligned manner.