Abstract: A traffic categorization method and device are disclosed. A traffic categorization method according to one embodiment of the present invention may comprise the steps of: receiving flow data comprising information about a flow; scaling for the flow data; generating input data by removing, on the basis of a correlation, overlapping data from the scaled flow data; and categorizing a network traffic on the basis of the input data.

Abstract: An electronic device is provided that includes a first display and a second display. The electronic device also includes a processor configured to allocate a first set of resources to the first display and a second set of resources to the second display. The first set of resources is different from the second set of resources. Each of the first set of resources and the second set of resources includes one or more of at least one available hardware resource and at least one available software resource.

Abstract: Address transforming methods are provided. The methods may include generating a power-up signal when a semiconductor memory device is powered-up. The methods may further include generating a randomized output signal in response to the power-up signal. The methods may additionally include transforming bits of a first address in response to the randomized output signal to generate a second address.

Abstract: A delay-locked loop (DLL) circuit capable of decreasing power consumption is provided. A DLL circuit includes a delay line, an output buffer, a replica circuit, a phase detector, a shift register and a replica control circuit. The delay line delays an external clock signal for a determined time to generate a first signal. The output buffer buffers the first signal to generate an internal clock signal. The replica circuit delays the first signal for a determined time to generate a feedback signal. The phase detector compares the feedback signal with the external clock signal to generate a shift control signal. The shift register performs a shifting operation based on the shift control signal to generate the plurality of delay control bits. The replica control circuit generates a replica control signal based on the external clock signal and a lock signal, to control the replica circuit.