Abstract: A dividing apparatus and method using coordinate rotation is disclosed. To this end, a plurality of rotation stages are sequentially performed until a divisor reaches a criterion and a rotation direction used in each of the plurality of stages is output. A division result acquired by performing rotation with respect to a dividend using the rotation direction for each of the plurality of stages is output.

Abstract: Provided is an apparatus and method for calibrating an imbalance characteristic of a received signal of a frequency domain in a mobile receiver which supports an Orthogonal Frequency Division Multiplexing (OFDM) scheme. To this end, a received signal of a radio frequency band is converted into a baseband signal by using a carrier, and the baseband received signal is converted from a time domain signal to a frequency domain signal. Then, a calibration coefficient is measured by using two consecutively received signals from the Fast Fourier Transform (FFT) unit. An imbalance component included in the received signal of the frequency domain due to an imbalance of the carrier is removed by using the measured calibration coefficient. In this case, the two consecutively received signals refer to two transmission signals consecutively transmitted from a transmitter, and the two transmission signals are predetermined signals.

Abstract: Disclosed is a method and an apparatus for self-calibrating a Direct Current (DC) offset and an imbalance between orthogonal signals, which may occur in a mobile transceiver. In the apparatus, a transmitter of a mobile terminal functions as a signal generator, and a receiver of the mobile terminal functions as a response characteristic detector. Further, a baseband processor applies test signals to the transmitter, receives the test signals returning from the receiver, and compensates the imbalance and DC offset for the transmitter side and the receiver side by using the test signals. The test signal is applied to only one of the I channel path and the Q channel path, and an RF band signal output from the transmission side by the test signal is used as an input signal to the reception side.

Abstract: A method is provided for self-calibrating the mismatch and the direct current (DC) offset occurring in a mobile transceiver. The transmitter of the mobile terminal is used as a signal generator and the receiver thereof is used as a response characteristic measurer. The baseband processor calibrates the mismatch and the DC offset for the receiving and transmitting sides using a test signal received from the transmitter. When multiple input subcarriers are used in a mixer present on a reception stage, self-calibration is performed using multiple received test signals obtained from one transmission test signal.

Abstract: Disclosed is a method and an apparatus for self-calibrating direct current (DC) offset and imbalance between orthogonal signals, which may occur in a mobile transceiver. In the apparatus, a transmitter of a mobile terminal functions as a signal generator, and a receiver of the mobile terminal functions as a response characteristic detector. Further, a baseband processor applies test signals to the transmitter, receives the test signals returning from the receiver, and compensates the imbalance and DC offset for the transmitter side and the receiver side by using the test signals.

Abstract: Provided is a coding/decoding apparatus for an orthogonal frequency division multiple access (OFDMA) communication system that takes multiple users into consideration and uses block coding/decoding scheme. In the apparatus, a mapper determines paths through which information of users will be provided, according to states of sub-channels allocated to the users. A coding/decoding unit parallel-processes the information of the users through the paths selectively connected by the mapper. The coding/decoding unit includes coders/decoders having performance lower than the maximum processing performance determined taking into account a size of a processing block and the number of sub-channels.

Abstract: Provided is a synchronization apparatus and method for a receiver that performs synchronization in a digital domain and detects a transmission signal. The synchronization apparatus includes an Analog-to-Digital (A/D) converter for converting a received signal into a digital signal, a frequency synchronizer for synchronizing a frequency using the digital signal output from the A/D converter, a signal detection unit for detecting a transmission symbol from a signal synchronized by the frequency synchronizer, and a residual phase detector for compensating for a residual phase of the transmission symbol output from the signal detection unit and outputting the resulting transmission symbol. The frequency synchronizer is capable of accurately and efficiently compensating for a frequency offset by minimizing the time delay caused by subcarrier synchronization using an improved CORDIC algorithm.

Abstract: An apparatus and a method for setting a routing path in System-on-a-Chip (SoC) having an n×n net topology-based structure comprising a plurality of intellectual properties (IPs), each with a unique address, and a plurality of switches forming one-to-one correspondence to the IPs, to transmit and receive data between the IPs by using at least one of the switches. Accordingly, an orthogonal code having orthogonality is assigned according to the direction of transmission of each data (that is, output port). Then, an output port where the data is transmitted is determined, and the data is spread based on an orthogonal code assigned to the output ports of the at least one of the switches.

Abstract: A method of establishing a path between routers in a system-on-chip (SoC) of n×n mesh topology structure having a plurality of intellectual properties (IPs) each with a unique address and routers corresponding to each of the IPs respectively, including: receiving a routing packet including a hop counter, and updating address information and information of a stored routing table; establishing a path to at least one neighboring router using the updated routing table upon a request to establish the path; and delivering data by using the established path.

Abstract: The present invention provides an effective method for mechanically removing iron oxide films formed on the surfaces of a hot rolled steel strip with a high temperature. The method comprises the steps of: maintaining a steel strip coil at a high temperature of 400° C. or more until the phase transformation is completed, after hot rolling; water-cooling the steel strip coil at a speed of at least 50° C./sec to 100° C. or less while uncoiling the coil; correcting the shape of the steel strip using a correction rolling mill; removing oxide films formed on surfaces of the shape-corrected steel strip by injecting water jets to the surface; and drying the steel strip free of oxide films and winding the steel strip. Also, the present invention provides an apparatus for carrying out this method.

Abstract: The present invention provides an effective method for mechanically removing iron oxide films formed on surfaces of a hot rolled steel strip with a high temperature.

Abstract: A method of manufacturing a cathode ray tube comprising the steps of providing a stem with a flange having an outer diameter larger than an inner diameter of a bottom end of a neck and smaller than or identical with an outer diameter of the bottom end of the neck, applying a liquefied frit glass onto an upper portion of the flange, hardening the liquefied frit glass applied on the upper portion of the flange, mounting an electron gun onto the stem, fitting the stem into the inside of the neck such that the upper portion of the flange applied with the frit glass contacts a bottom end of the neck, and providing a frit seal between the upper portion of the flange and the bottom end of the neck by heat-treating the frit glass between them.

Abstract: The present invention relates to a digital phase correcting apparatus, including a phase comparator (100), a loop filter (110), and a digital controlled oscillator (120). The digital controlled oscillator (120) includes a phase clock signal generator (400), a multiplexer (410), an up/down counter (430), and a frequency divider (420). The phase clock signal generator (400) receives the master clock signal as an input and generates therefrom a plurality of clock signals having a phase difference of half a period of the master clock signal. The multiplexer (410) selects and outputs one of the clock signals generated in the phase clock signal generator (400). The up/down counter (430) receiving a phase lead/lag signal of the loop filter (110) and provides an output select signal for the multiplexer (410). The frequency divider divides the frequency of the clock signal output from the multiplexer and outputting the phase locked clock signal to the phase comparator.