Abstract: A semiconductor device having many pins is tested using a test system having fewer pins. The test system includes a pin electronics (PE) card and a pattern memory. The PE card preferably includes a plurality of comparator and driver units to drive predetermined input signal pattern to be applied to an input pin of the semiconductor device and to compare data output from an output pin of the semiconductor device with a predetermined output signal pattern. Some or all of the pins of the semiconductor device may be divided into pin groups having K number of pins. The PE card also preferably includes a plurality of control units for electrically connecting each of the comparator and driver units to a selected pin in a selected pin group in response to a control signal.

Abstract: A test apparatus simultaneously tests a plurality of semiconductor integrated circuits according to test data stored in a single memory set. A sub-test data generator includes a plurality of data reproduction units, each of which corresponds to one of the integrated circuits being tested. Each data reproduction unit reproduces the stored test data into a reproduced test data set, which is then processed by a driver, and sent to the corresponding integrated circuit for testing.

Abstract: A test apparatus simultaneously tests a plurality of semiconductor integrated circuits according to test data stored in a single memory set. A sub-test data generator includes a plurality of data reproduction units, each of which corresponds to one of the integrated circuits being tested. Each data reproduction unit reproduces the stored test data into a reproduced test data set, which is then processed by a driver, and sent to the corresponding integrated circuit for testing.

Abstract: According to various aspects and embodiments of this invention, a semiconductor device having many pins can effectively be tested using a test system having fewer pins. A semiconductor device test system and method are provided to effectively test a semiconductor device having many pins. The test system includes a pin electronics (PE) card and a pattern memory. The PE card preferably includes a plurality of comparator and driver units, wherein each comparator and driver unit can include a driver for driving a predetermined input signal pattern to be applied to an input pin of the semiconductor device and a comparator for comparing data output from an output pin of the semiconductor device with a predetermined output signal pattern. Some or all of the pins of the semiconductor device are divided into pin groups having K number of pins.