Abstract: Disclosed is a method for manufacturing a power semiconductor device. The method includes forming a lower active layer on a substrate, forming an upper active layer on both sides of the lower active layer, forming a source electrode, a drain electrode, and a gate electrode on the upper active layer and the lower active layer, and forming a heat dissipating and electrical ground electrode penetrating the substrate and the lower active layer and connected to a lower surface of the lower active layer. The upper active layer may be epitaxially grown at a high doping concentration by a selective deposition method using a mask layer that exposes a portion of the lower active layer as a blocking layer.

Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes: an active region provided on a substrate; an inlet channel formed as a single cavity buried in one side of the substrate; an outlet channel formed as a single cavity buried in the other side of the substrate; a micro channel array comprising a plurality of micro channels, wherein the plurality of micro channels are formed as a plurality of cavities buried in the substrate, and one end of the micro channel array is connected to a side of the inlet channel and the other end of the micro channel array is connected to a side of the outlet channel; and a micro heat sink array separating the micro channels from one another.

Abstract: A cascode switch circuit includes a first transistor, a second transistor, and a protector. A first transistor receives a signal from a first terminal through a first end and transfers the signal to a second end in response to a first control signal. A second transistor delivers the signal that the first transistor transfers to a second terminal in response to a second control signal. A protector is connected between a gate of the first transistor and the second terminal. The first control signal is provided to allow the first transistor to operate in a normally-on state. The second control signal is provided to allow the second transistor to operate in a normally-off state.

Abstract: A cascode switch circuit includes a first transistor, a second transistor, and a protector. A first transistor receives a signal from a first terminal through a first end and transfers the signal to a second end in response to a first control signal. A second transistor delivers the signal that the first transistor transfers to a second terminal in response to a second control signal. A protector is connected between a gate of the first transistor and the second terminal. The first control signal is provided to allow the first transistor to operate in a normally-on state. The second control signal is provided to allow the second transistor to operate in a normally-off state.

Abstract: A field effect transistor is provided. The field effect transistor may include a capping layer on a substrate, a source ohmic electrode and a drain ohmic electrode on the capping layer, a first insulating layer and a second insulating layer stacked on the capping layer to cover the source and drain ohmic electrodes, a ?-shaped gate electrode including a leg portion and a head portion, the leg portion being connected to the substrate between the source ohmic electrode and the drain ohmic electrode, and the head portion extending from the leg portion to cover a top surface of the second insulating layer, a first planarization layer on the second insulating layer to cover the ?-shaped gate electrode, and a first electrode on the first planarization layer, the first electrode being connected to the source ohmic electrode or the drain ohmic electrode.

Abstract: A first nitride semiconductor layer of a semiconductor device is provided on a substrate, a second nitride semiconductor layer is provided on the first nitride semiconductor layer, a first ohmic metal and a second ohmic metal are provided on the second nitride semiconductor layer, a recess region is provided in the second nitride semiconductor layer between the first ohmic metal and the second ohmic metal, a passivation layer covers side of the first ohmic metal and a bottom surface and sides of the recess region, and a Schottky electrode is provided on the first ohmic metal and extends into the recess region.

Abstract: A semiconductor device may include a substrate having a lower via-hole, an epitaxial layer having an opening exposing a top surface of the substrate, a semiconductor chip disposed on the top surface of the substrate and including first, second, and third electrodes, an upper metal layer connected to the first electrode, a supporting substrate disposed on the upper metal layer and having an upper via-hole, an upper pad disposed on the substrate and extending into the upper via-hole, a lower pad connected to the second electrode in the opening, and a lower metal layer covering a bottom surface of the substrate and connected to the lower pad through the lower via-hole.

Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes: an active region provided on a substrate; an inlet channel formed as a single cavity buried in one side of the substrate; an outlet channel formed as a single cavity buried in the other side of the substrate; a micro channel array comprising a plurality of micro channels, wherein the plurality of micro channels are formed as a plurality of cavities buried in the substrate, and one end of the micro channel array is connected to a side of the inlet channel and the other end of the micro channel array is connected to a side of the outlet channel; and a micro heat sink array separating the micro channels from one another.

Abstract: The inventive concept relates to a system supplying a constant current direct current power to serial loads connected in series with one another. The inventive concept is constituted by a constant current source power supply unit outputting a predetermined direct current, a load connection unit having the same rated current characteristic as the constant current source, a load connection unit having a rated current characteristic smaller than the constant current source, a load connection unit having a rated current characteristic greater than the constant current source, a load connection unit having a rated current characteristic greater or smaller than the constant current source and a circuit controlling or protecting them.

Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes: an active region provided on a substrate; an inlet channel formed as a single cavity buried in one side of the substrate; an outlet channel formed as a single cavity buried in the other side of the substrate; a micro channel array comprising a plurality of micro channels, wherein the plurality of micro channels are formed as a plurality of cavities buried in the substrate, and one end of the micro channel array is connected to a side of the inlet channel and the other end of the micro channel array is connected to a side of the outlet channel; and a micro heat sink array separating the micro channels from one another.

Abstract: A manufacturing method for a variable capacitor includes forming a first element of which a capacitance value depends on a voltage applied to both of two terminals of a first area on a substrate, forming a second element having a capacitance value fixed to a second area on the substrate adjacent to the first area, and forming metallic wires for connecting the first element and the second element and connecting the first element and the second element with the outside. The first element maybe a bipolar transistor that may include a diode. The second element maybe a capacitor that includes a dielectric.

Abstract: A semiconductor device may include a substrate having a lower via-hole, an epitaxial layer having an opening exposing a top surface of the substrate, a semiconductor chip disposed on the top surface of the substrate and including first, second, and third electrodes, an upper metal layer connected to the first electrode, a supporting substrate disposed on the upper metal layer and having an upper via-hole, an upper pad disposed on the substrate and extending into the upper via-hole, a lower pad connected to the second electrode in the opening, and a lower metal layer covering a bottom surface of the substrate and connected to the lower pad through the lower via-hole.

Abstract: A field effect transistor is provided. The transistor may include a source electrode and a drain electrode provided spaced apart from each other on a substrate and a ‘+’-shaped gate electrode provided on a portion of the substrate located between the source and drain electrodes.

Abstract: Disclosed is a manufacturing method of a high electron mobility transistor. The method includes: forming a source electrode and a drain electrode on a substrate; forming a first insulating film having a first opening on an entire surface of the substrate, the first opening exposing a part of the substrate; forming a second insulating film having a second opening within the first opening, the second opening exposing a part of the substrate; forming a third insulating film having a third opening within the second opening, the third opening exposing a part of the substrate; etching a part of the first insulating film, the second insulating film and the third insulating film so as to expose the source electrode and the drain electrode; and forming a T-gate electrode on a support structure including the first insulating film, the second insulating film and the third insulating film.

Abstract: Provided is a feedback amplifier. The feedback amplifier includes: an amplification circuit unit amplifying a burst packet signal inputted from an input terminal and outputting the amplified voltage to an output terminal; a feedback circuit unit disposed between the input terminal and the output terminal and controlling whether to apply a fixed resistance value to a signal outputted to the output terminal; a packet signal detection unit detecting a peak value of a burst packet signal from the output terminal and controlling whether to apply the fixed resistance value; and a bias circuit unit generating a bias voltage, wherein the feedback circuit unit determines a feedback resistance value to change the fixed resistance value in response to at least one control signal and adjusts a gain by receiving the bias voltage.

Abstract: A semiconductor device may include a substrate having a lower via-hole, an epitaxial layer having an opening exposing a top surface of the substrate, a semiconductor chip disposed on the top surface of the substrate and including first, second, and third electrodes, an upper metal layer connected to the first electrode, a supporting substrate disposed on the upper metal layer and having an upper via-hole, an upper pad disposed on the substrate and extending into the upper via-hole, a lower pad connected to the second electrode in the opening, and a lower metal layer covering a bottom surface of the substrate and connected to the lower pad through the lower via-hole.

Abstract: Provided is a method of manufacturing a nitride semiconductor device. The method includes forming a plurality of electrodes on a growth substrate on which first and second nitride semiconductor layers are sequentially stacked, forming upper metal layers on the plurality of electrodes respectively, removing the growth substrate to expose a lower surface of the first nitride semiconductor layer, and forming a third nitride semiconductor layer and a lower metal layer sequentially on the exposed lower surface of the first nitride semiconductor layer.

Abstract: Provided is a nitride semiconductor device including: a substrate having through via holes; first and second nitride semiconductor layers sequentially stacked on the substrate; drain electrodes and source electrodes provided on the second nitride semiconductor layer; and an insulating pattern provided on the second nitride semiconductor layer, the insulating pattern having upper via holes provided on the drain electrodes, wherein the through via holes are extended into the first and second nitride semiconductor layers and expose a bottom of each of the source electrodes.

Abstract: A method of manufacturing a semiconductor device includes forming devices including source, drain and gate electrodes on a front surface of a substrate including a bulk silicon, a buried oxide layer, an active silicon, a gallium nitride layer, and an aluminum-gallium nitride layer sequentially stacked, etching a back surface of the substrate to form a via-hole penetrating the substrate and exposing a bottom surface of the source electrode, conformally forming a ground interconnection on the back surface of the substrate having the via-hole, forming a protecting layer on the front surface of the substrate, and cutting the substrate to separate the devices from each other.

Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes: an active region provided on a substrate; an inlet channel formed as a single cavity buried in one side of the substrate; an outlet channel formed as a single cavity buried in the other side of the substrate; a micro channel array comprising a plurality of micro channels, wherein the plurality of micro channels are formed as a plurality of cavities buried in the substrate, and one end of the micro channel array is connected to a side of the inlet channel and the other end of the micro channel array is connected to a side of the outlet channel; and a micro heat sink array separating the micro channels from one another.