Abstract: Structures including an electro-optic bridge chip and methods of forming such structures. The structure comprises a photonics chip and an electro-optic bridge chip on a package substrate. The electro-optic bridge chip includes a waveguide core and an electrical trace line. A portion of the waveguide core is coupled to an optical coupler of the photonics chip.

Abstract: Structures for a co-packaged photonics chip and electronic chip, and associated methods. The structure comprises a layer comprising a molding compound, an electronic chip and a photonics chip affixed in the layer, and a waveguiding structure including a waveguide core adjacent to the photonics chip. The photonics chip includes an optical coupler, the waveguide core includes a portion that overlaps with the optical coupler, and the waveguide core comprises a polymer.

Abstract: A photonic integrated circuit (PIC) structure includes an active region in at least an active layer over a substrate, the active region including a plurality of transistors therein. A plurality of dielectric interconnect layers are over the active region, and an opening is defined through the plurality of dielectric interconnect layers. The opening extends to at least the active layer. A barrier is within the plurality of dielectric interconnect layers and surrounding the opening. An optical element is positioned in the opening. The barrier prevents stress damage, such as cracks and/or delaminations, from propagating from or to the opening, and maintains the hermetic seal of the PIC structure.

Abstract: Embodiments of the disclosure provide a photonic integrated circuit (PIC) structure with a passage for a waveguide through a barrier structure. The PIC structure includes a barrier structure on a substrate, having a first sidewall and a second sidewall opposite the first sidewall. A passage is within the barrier structure, and extends from a first end at the first sidewall of the barrier structure to a second end at the second sidewall of the barrier structure. A shape of the passage includes a reversal segment between the first end and the second end. A waveguide within the passage and extends from the first end to the second end of the barrier structure.

Abstract: A photonic integrated circuit (PIC) structure includes an active region in at least an active layer over a substrate, the active region including a plurality of transistors therein. A plurality of dielectric interconnect layers are over the active region, and an opening is defined through the plurality of dielectric interconnect layers. The opening extends to at least the active layer. A barrier is within the plurality of dielectric interconnect layers and surrounding the opening. An optical element is positioned in the opening. The barrier prevents stress damage, such as cracks and/or delaminations, from propagating from or to the opening, and maintains the hermetic seal of the PIC structure.

Abstract: Structures for an optical fiber groove and methods of forming a structure for an optical fiber groove. A photonics chip includes a substrate and an interconnect structure over the substrate. The photonics chip has a first exterior corner, a second exterior corner, and a side edge extending from the first exterior corner to the second exterior corner. The substrate includes a groove positioned along the side edge between the first exterior corner and the second exterior corner. The groove is arranged to intersect the side edge at a groove corner, and the interconnect structure includes metal structures adjacent to the first groove corner. The metal structures extend diagonally in the interconnect structure relative to the side edge of the photonics chip.

Abstract: Structures including an edge coupler and a crackstop, as well as methods of forming a structure including an edge coupler and a crackstop. A waveguide core and a crackstop are located over a top surface of a dielectric layer. A communication passageway is either optically coupled or electrically coupled to the waveguide core. The communication passageway, which may include an electric conductor or a buried waveguide core, extends laterally beneath the crackstop.

Abstract: Embodiments of the disclosure provide a photonic integrated circuit (PIC) structure with a passage for a waveguide through a barrier structure. The PIC structure includes a barrier structure on a substrate, having a first sidewall and a second sidewall opposite the first sidewall. A passage is within the barrier structure, and extends from a first end at the first sidewall of the barrier structure to a second end at the second sidewall of the barrier structure. A shape of the passage includes a reversal segment between the first end and the second end. A waveguide within the passage and extends from the first end to the second end of the barrier structure.

Abstract: Structures including an edge coupler and a crackstop, as well as methods of forming a structure including an edge coupler and a crackstop. A waveguide core and a crackstop are located over a top surface of a dielectric layer. A communication passageway is either optically coupled or electrically coupled to the waveguide core. The communication passageway, which may include an electric conductor or a buried waveguide core, extends laterally beneath the crackstop.

Abstract: Structures for an optical fiber groove and methods of forming a structure for an optical fiber groove. A photonics chip includes a substrate and an interconnect structure over the substrate. The photonics chip has a first exterior corner, a second exterior corner, and a side edge extending from the first exterior corner to the second exterior corner. The substrate includes a groove positioned along the side edge between the first exterior corner and the second exterior corner. The groove is arranged to intersect the side edge at a groove corner, and the interconnect structure includes metal structures adjacent to the first groove corner. The metal structures extend diagonally in the interconnect structure relative to the side edge of the photonics chip.

Abstract: Structures for an optical fiber groove and methods of forming a structure for an optical fiber groove. A photonics chip includes a substrate and an interconnect structure over the substrate. The photonics chip has a first exterior corner, a second exterior corner, and a side edge extending from the first exterior corner to the second exterior corner. The substrate includes a groove positioned along the side edge between the first exterior corner and the second exterior corner. The groove is arranged to intersect the side edge at a groove corner, and the interconnect structure includes metal structures adjacent to the first groove corner. The metal structures extend diagonally in the interconnect structure relative to the side edge of the photonics chip.

Abstract: Structures for an optical fiber groove and methods of forming a structure for an optical fiber groove. A photonics chip includes a substrate and an interconnect structure over the substrate. The photonics chip has a first exterior corner, a second exterior corner, and a side edge extending from the first exterior corner to the second exterior corner. The substrate includes a groove positioned along the side edge between the first exterior corner and the second exterior corner. The groove is arranged to intersect the side edge at a groove corner, and the interconnect structure includes metal structures adjacent to the first groove corner. The metal structures extend diagonally in the interconnect structure relative to the side edge of the photonics chip.

Abstract: A method for providing a geo-fence service using a map provided via a navigation device includes: searching for at least one critical route from a current position of a vehicle or an origin to a destination mapped onto the map; displaying a first critical route onto the map along the vehicle can travel to the destination, the first critical route corresponding to a shortest route among the at least one searched critical route; and determining whether the vehicle deviates from a geo-fence area including the at least one searched critical route.

Abstract: A method for providing a geo-fence service using a map provided via a navigation device includes: searching for at least one critical route from a current position of a vehicle or an origin to a destination mapped onto the map; displaying a first critical route onto the map along the vehicle can travel to the destination, the first critical route corresponding to a shortest route among the at least one searched critical route; and determining whether the vehicle deviates from a geo-fence area including the at least one searched critical route.

Abstract: Methods for forming a dummy metal structure between dies on a semiconductor wafer and the resulting devices are disclosed. Embodiments may include forming metal interconnection layers extending from a substrate of a semiconductor wafer to a top metal interconnection layer of the semiconductor wafer between a plurality of die regions, each of the metal interconnection layers including a plurality of dummy vertical interconnect accesses (VIAs) and a plurality of dummy metal lines, with the plurality of dummy metal lines laterally connecting the plurality of dummy VIAs within each respective metal interconnection layer, and a plurality of dummy VIAs within a first metal interconnection layer vertically connecting a plurality of dummy metal lines within the first metal interconnection layer to a plurality of dummy metal lines within a second metal interconnection layer, and the second metal interconnection layer being below the first metal interconnection layer.

Abstract: Methods for forming a dummy metal structure between dies on a semiconductor wafer and the resulting devices are disclosed. Embodiments may include forming metal interconnection layers extending from a substrate of a semiconductor wafer to a top metal interconnection layer of the semiconductor wafer between a plurality of die regions, each of the metal interconnection layers including a plurality of dummy vertical interconnect accesses (VIAs) and a plurality of dummy metal lines, with the plurality of dummy metal lines laterally connecting the plurality of dummy VIAs within each respective metal interconnection layer, and a plurality of dummy VIAs within a first metal interconnection layer vertically connecting a plurality of dummy metal lines within the first metal interconnection layer to a plurality of dummy metal lines within a second metal interconnection layer, and the second metal interconnection layer being below the first metal interconnection layer.

Abstract: Methods for forming a dummy metal structure between dies on a semiconductor wafer and the resulting devices are disclosed. Embodiments may include forming metal interconnection layers extending from a substrate of a semiconductor wafer to a top metal interconnection layer of the semiconductor wafer between a plurality of die regions, each of the metal interconnection layers including a plurality of dummy vertical interconnect accesses (VIAs) and a plurality of dummy metal lines, with the plurality of dummy metal lines laterally connecting the plurality of dummy VIAs within each respective metal interconnection layer, and a plurality of dummy VIAs within a first metal interconnection layer vertically connecting a plurality of dummy metal lines within the first metal interconnection layer to a plurality of dummy metal lines within a second metal interconnection layer, and the second metal interconnection layer being below the first metal interconnection layer.

Abstract: Methods for forming a dummy metal structure between dies on a semiconductor wafer and the resulting devices are disclosed. Embodiments may include forming metal interconnection layers extending from a substrate of a semiconductor wafer to a top metal interconnection layer of the semiconductor wafer between a plurality of die regions, each of the metal interconnection layers including a plurality of dummy vertical interconnect accesses (VIAs) and a plurality of dummy metal lines, with the plurality of dummy metal lines laterally connecting the plurality of dummy VIAs within each respective metal interconnection layer, and a plurality of dummy VIAs within a first metal interconnection layer vertically connecting a plurality of dummy metal lines within the first metal interconnection layer to a plurality of dummy metal lines within a second metal interconnection layer, and the second metal interconnection layer being below the first metal interconnection layer.

Abstract: Compositions that have relatively high Tg, relatively low CTE, and relatively low modulus are suitable for use as encapsulants with stress-sensitive electronic assemblies, such as those containing low k dielectrics. These compositions are used in methods of die attachment, encapsulation, and solder bump reinforcement.

Abstract: The present invention relates to a digital multimedia broadcasting reception system and method, and in particular to, a technology for transmitting a digital multimedia broadcasting signal received in a tuner to a head unit without a compression process.