Abstract: A semiconductor package includes a film substrate; a wiring layer provided on the film substrate; and a semiconductor chip provided on the wiring layer and electrically connected to the wiring layer. The film substrate includes a first layer, wherein the first layer is an insulating layer having the wiring layer thereon. The film substrate further includes a second layer, wherein the second layer is attached to a bottom of the first layer and comprises a gas. The second layer is configured to be peeled off of the first layer.

Abstract: A chip-on-film package may include a film substrate including a chip region and an edge region, a semiconductor chip provided on the chip region and mounted on a top surface of the film substrate, the semiconductor chip including a chip pad adjacent to a bottom surface thereof, an input line and an output line provided on the edge region and disposed on the top surface of the film substrate, a connection terminal interposed between the film substrate and the semiconductor chip, and a redistribution pattern disposed between the semiconductor chip and the connection terminal.

Abstract: A connection structure of a stator of a drive motor is configured to allow coils to be wound in a plurality of slots provided in a stator core and to connect the coils withdrawn from the slots. The coils are wound in the slots to form first-type structures and second-type structures configured such that withdrawal directions of three-phase (U-, W- and V-phase) withdrawal lines and N-phase withdrawal lines withdrawn from the slots of the first-type structures are opposite to withdrawal directions of three-phase (U-, W- and V-phase) withdrawal lines and N-phase withdrawal lines withdrawn from the slots of the second-type structures. The first-type structures and the second-type structures are disposed symmetrically to each other with respect to a reference line formed to divide the slots in half.

Abstract: In a thin layer structure and a method of forming the same, a first preliminary insulation pattern is formed on a substrate and includes a first opening exposing the substrate. One or more preliminary seed patterns including single crystalline silicon are formed in the first opening. A second insulation layer is formed on the first preliminary insulation pattern and the one or more preliminary seed patterns. A second insulation pattern, a first insulation pattern and one or more seed patterns are formed by etching the first and second insulation layers and the one or more preliminary seed patterns. The second insulation pattern includes a second opening having a flat bottom portion. A single crystalline silicon pattern is formed in the second opening, wherein a central thickness of the single crystalline silicon pattern is substantially identical to a peripheral thickness thereof, thereby reducing or preventing a thinning defect in a semiconductor device.

Abstract: A double pattern method of forming a plurality of contact holes in a material layer formed on a substrate is disclosed. The method forms a parallel plurality of first hard mask patterns separated by a first pitch in a first direction on the material layer, a self-aligned parallel plurality of second hard mask patterns interleaved with the first hard mask patterns and separated from the first hard mask patterns by a buffer layer to form composite mask patterns, and a plurality of upper mask patterns in a second direction intersecting the first direction to mask selected portions of the buffer layer in conjunction with the composite mask patterns. The method then etches non-selected portions of the buffer layer using the composite hard mask patterns and the upper mask patterns as an etch mask to form a plurality of hard mask holes exposing selected portions of the material layer, and then etches the selected portions of the material layer to form the plurality of contact holes.

Abstract: A double pattern method of forming a plurality of contact holes in a material layer formed on a substrate is disclosed. The method forms a parallel plurality of first hard mask patterns separated by a first pitch in a first direction on the material layer, a self-aligned parallel plurality of second hard mask patterns interleaved with the first hard mask patterns and separated from the first hard mask patterns by a buffer layer to form composite mask patterns, and a plurality of upper mask patterns in a second direction intersecting the first direction to mask selected portions of the buffer layer in conjunction with the composite mask patterns. The method then etches non-selected portions of the buffer layer using the composite hard mask patterns and the upper mask patterns as an etch mask to form a plurality of hard mask holes exposing selected portions of the material layer, and then etches the selected portions of the material layer to form the plurality of contact holes.

Abstract: Methods are provided for forming a device, such as a semiconductor device. A field region and an active region of a substrate are defined in which the field region has an upper surface that extends further away from the substrate and is higher than an upper surface of the active region. A hard mask layer is formed with a substantially planar upper surface on the field region and the active region. The hard mask layer is partially etched to form a hard mask pattern that exposes at least a portion of the active region. The substrate is partially etched in the active region using the hard mask pattern as an etching mask to form a gate trench. A recessed gate electrode if formed on the substrate in the gate trench.

Abstract: In a thin layer structure and a method of forming the same, a first preliminary insulation pattern is formed on a substrate and includes a first opening exposing the substrate. One or more preliminary seed patterns including single crystalline silicon are formed in the first opening. A second insulation layer is formed on the first preliminary insulation pattern and the one or more preliminary seed patterns. A second insulation pattern, a first insulation pattern and one or more seed patterns are formed by etching the first and second insulation layers and the one or more preliminary seed patterns. The second insulation pattern includes a second opening having a flat bottom portion. A single crystalline silicon pattern is formed in the second opening, wherein a central thickness of the single crystalline silicon pattern is substantially identical to a peripheral thickness thereof, thereby reducing or preventing a thinning defect in a semiconductor device.

Abstract: Methods are provided for forming a device, such as a semiconductor device. A field region and an active region of a substrate are defined in which the field region has an upper surface that extends further away from the substrate and is higher than an upper surface of the active region. A hard mask layer is formed with a substantially planar upper surface on the field region and the active region. The hard mask layer is partially etched to form a hard mask pattern that exposes at least a portion of the active region. The substrate is partially etched in the active region using the hard mask pattern as an etching mask to form a gate trench. A recessed gate electrode if formed on the substrate in the gate trench.

Abstract: Embodiments of the invention include dynamic random access memory (DRAM) devices that utilize field effect transistors with trench-based gate electrodes. In these devices, a semiconductor substrate is provided having an isolation trench therein. This isolation trench is formed in a first portion of the semiconductor substrate. An electrically insulating liner is provided on a bottom and sidewalls of the isolation trench. The isolation trench is also filled with field oxide region, which extends on the electrically insulating liner. A field effect transistor is also provided in the semiconductor substrate. This transistor includes a gate electrode trench in a second portion of the semiconductor substrate and a gate insulating layer that lines a bottom and sidewalls of the gate electrode trench. A gate electrode is provided in the gate electrode trench. The gate electrode contacts the electrically insulating liner in the isolation trench and the gate insulating layer.