Abstract: A method of forming patterns of a semiconductor device, including partially etching an upper portion of a substrate to form first preliminary active patterns and a first trench, each of the first preliminary active patterns having a first width, and the first trench having a second width of about 2 to 3 times the first width; forming an insulating spacer on each sidewall of the first trench to form a second trench having the first width; forming a second preliminary active pattern in the second trench, the second preliminary active pattern having the first width; partially etching the first and second preliminary active patterns to form a plurality of first active patterns and a plurality of second active patterns and an opening between the plurality of first and second active patterns; and forming an insulation pattern to fill the opening.

Abstract: A semiconductor device includes a substrate, first and second isolation layers, an insulation layer pattern, and a gate structure. The substrate has a cell region and a peripheral region. The first isolation layer is buried in a first upper portion of the substrate in the peripheral region. The second isolation layer is buried in a second upper portion of the substrate in the cell region, and extends along a first direction substantially parallel to a top surface of the substrate. The insulation layer pattern is buried in the first upper portion, and extends along a second direction substantially parallel to the top surface of the substrate and substantially perpendicular to the first direction. The insulation layer pattern has a lower surface higher than a lower surface of the second isolation layer, and applies a stress to a portion of the substrate adjacent thereto.

Abstract: A gear train layout structure may include a fuel pump configured to pressurize fuel and to supply the pressurized fuel to an engine, a pump shaft, a driven gear for rotating the pump shaft, a driving gear to drive the driven gear, a first balance shaft and a second balance shaft respectively mounted at a front and a rear of a crankshaft of the engine for balancing the engine and attenuating vibration of the engine, a first balance gear and a second balance gear, a crank gear fixedly mounted on a side portion of the crankshaft, and at least one connecting rod connecting the crankshaft and a piston for rotating the crankshaft.

Abstract: A resistive memory device includes a cell block having a plurality of unit memory cells in which a resistive element and a cell select element are connected to each other in series, the cell block operating in response to a word line, a bit line, and a source line, and a dummy line, when different interconnection layers form the source line and the bit line, respectively, connected to one of the interconnection layers which is formed at a lower side the remaining interconnection layer between the interconnection layers for the source line and the bit line, wherein the dummy line has a resistance lower than a resistance of the lower interconnection layer.

Abstract: The magnetic memory device includes a plurality of source lines arranged in parallel in a second direction orthogonal to a first direction while extending in the first direction on a substrate, a plurality of word lines arranged in parallel in the first direction while extending in the second direction on the substrate, a plurality of bit lines arranged in parallel in the second direction while extending in the first direction on the substrate to alternate with the plurality of source lines, and a plurality of active regions arranged to extend at an oblique angle with respect to the first direction and arranged so that one memory cell is selected when one of the plurality of word lines and one of the plurality of source lines or the plurality of bit lines are selected.

Abstract: A magnetic memory device is provided. The magnetic memory device includes a substrate including a first source/drain region and a second source/drain region; a word line structure between the first and source/drain regions and extending in a first direction; a buried contact electrically connected to the first source/drain region and on the first source/drain region; a contact pad electrically connected to the buried contact and on the buried contact; and a memory portion electrically connected to the contact pad and on the contact pad, the contact pad including a metal silicide layer.

Abstract: Memory systems can include a memory device having an array of nonvolatile memory cells therein, which is electrically coupled to a plurality of bit lines and a plurality of word lines. The nonvolatile memory cells may include respective nonvolatile resistive devices electrically coupled in series with corresponding cell transistors. A controller is also provided, which may be coupled to the memory device. The controller can be configured to drive the memory device with signals that support dual programming of: (i) the nonvolatile resistive devices; and (ii) interface states within the cell transistors, during operations to write data into the memory device.

Abstract: Memory systems can include a memory device having an array of nonvolatile memory cells therein, which is electrically coupled to a plurality of bit lines and a plurality of word lines. The nonvolatile memory cells may include respective nonvolatile resistive devices electrically coupled in series with corresponding cell transistors. A controller is also provided, which may be coupled to the memory device. The controller can be configured to drive the memory device with signals that support dual programming of: (i) the nonvolatile resistive devices; and (ii) interface states within the cell transistors, during operations to write data into the memory device.

Abstract: An apparatus and a method for maximizing debugging performance and reducing memory overhead are provided. The method includes generating a debug protocol packet and transmitting the generated debug protocol packet to a diagnostic device. The debug protocol packet includes reference information for at least one string associated with a debug trace.

Abstract: A resistive memory device includes a memory cell array, an input/output (I/O) sense amplifier unit, an address input buffer, a row decoder, and a column decoder. The memory cell array includes unit memory cells, and operates in response to a word line driving signal and a column selecting signal, each unit memory cell includes a resistive device and a compensation resistive device. The I/O sense amplifier unit amplifies data output from the memory cell array to generate first data, and transfers input data to the memory cell array. The address input buffer generates a row address signal and a column address signal based on an external address. The row decoder decodes the row address signal and generates the word line driving signal based on the decoded row address signal. The column decoder decodes the column address signal and generates the column selecting signal based on the decoded column address signal.

Abstract: The magnetic memory device includes a plurality of source lines arranged in parallel in a second direction orthogonal to a first direction while extending in the first direction on a substrate, a plurality of word lines arranged in parallel in the first direction while extending in the second direction on the substrate, a plurality of bit lines arranged in parallel in the second direction while extending in the first direction on the substrate to alternate with the plurality of source lines, and a plurality of active regions arranged to extend at an oblique angle with respect to the first direction and arranged so that one memory cell is selected when one of the plurality of word lines and one of the plurality of source lines or the plurality of bit lines are selected.

Abstract: A resistive memory device includes a cell block having a plurality of unit memory cells in which a resistive element and a cell select element are connected to each other in series, the cell block operating in response to a word line, a bit line, and a source line, and a dummy line, when different interconnection layers form the source line and the bit line, respectively, connected to one of the interconnection layers which is formed at a lower side the remaining interconnection layer between the interconnection layers for the source line and the bit line, wherein the dummy line has a resistance lower than a resistance of the lower interconnection layer.

Abstract: Memory systems can include a memory device having an array of nonvolatile memory cells therein, which is electrically coupled to a plurality of bit lines and a plurality of word lines. The nonvolatile memory cells may include respective nonvolatile resistive devices electrically coupled in series with corresponding cell transistors. A controller is also provided, which may be coupled to the memory device. The controller can be configured to drive the memory device with signals that support dual programming of: (i) the nonvolatile resistive devices; and (ii) interface states within the cell transistors, during operations to write data into the memory device.

Abstract: A semiconductor device includes a first semiconductor layer extending in a first direction on a substrate, a plurality of second semiconductor layers spaced apart in the first direction on the first semiconductor layer, and an insulation layer structure surrounding side walls of the first semiconductor layer and the plurality of second semiconductor layers. The first semiconductor layer may have a first conductivity type, and the plurality of second semiconductor layers may have a second conductivity type.

Abstract: A guide plate mounting structure of a fuel pump, the guide plate mounting structure may include a fuel pump having a housing, a driving shaft protrudedly formed from the housing to the outside of the fuel pump, a block mounted onto an outer peripheral surface of the housing of the fuel pump, a guide plate having a first through hole formed at a center thereof and being positioned at an end of the block, and a fuel pump gear having a second through hole formed at a center thereof and being mounted to the driving shaft of the fuel pump through the second through hole, and a rim formed on an end surface of the fuel pump gear so as to be inserted into a first end surface of the guide plate.

Abstract: An apparatus and a method for automated testing of electrostatic discharge of a Device Under Test (DUT) are provided. In the apparatus and the method, an electrostatic pulse is applied to the DUT, a malfunction type is detected from the DUT, and a control command is transmitted to the DUT to return a test mode of the DUT to a normal mode according to the detected malfunction type.

Abstract: A shield apparatus for an electronic device includes: an electronic device case; a printed circuit board; a shield member mounted on a location of the printed circuit board; and at least one shield unit provided on the shield member to contact the electronic device case and be resiliently pressed by the electronic device case such that the shield member is coupled with the electronic device case.

Abstract: An illuminator of a door outside handle for a vehicle may perform both a function of a light source and a light guiding function. The illuminator may further employ a light guide having a mood lamp function on an inner surface of the door outside handle and a top LED combined with the light guide to illuminate the outer panel together with the illuminator, making it possible to enhance a product value due to realization of various illumination effects. The illuminator of a door outside handle for a vehicle can be turned on or off through various operation logics by employing multiple different illumination methods where lights of different colors can be realized according to the operation condition, making it possible to enhance product value.

Abstract: An image reading device having an improved shading compensation capability and a method thereof are disclosed. The image reading device includes an automatic document feed unit to deliver documents along a document delivery path. A light source unit including a light source to illuminate a first criterion image at a first position within the image reading device, and to illuminate the documents delivered by the automatic document feed unit at a second position. The image reading device further includes a second criterion image arranged to opposingly face the light source unit when the light source unit is located at the second position. The second criterion image extends along a sufficient length to cover the scanning range of the light illumination by the light source unit along a main scanning direction.

Abstract: A resistive memory device includes a memory cell array, an input/output (I/O) sense amplifier unit, an address input buffer, a row decoder, and a column decoder. The memory cell array includes unit memory cells, and operates in response to a word line driving signal and a column selecting signal, each unit memory cell includes a resistive device and a compensation resistive device. The I/O sense amplifier unit amplifies data output from the memory cell array to generate first data, and transfers input data to the memory cell array. The address input buffer generates a row address signal and a column address signal based on an external address. The row decoder decodes the row address signal and generates the word line driving signal based on the decoded row address signal. The column decoder decodes the column address signal and generates the column selecting signal based on the decoded column address signal.