Patents by Inventor Jae-Kyun Kim

Jae-Kyun Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220177668
    Abstract: The present invention pertains to a method for producing high value-added compounds from polyethylene terephthalate. More specifically, the present invention demonstrates that a monomeric terephthalic acid obtained from the chemical hydrolysis of polyethylene terephthalate can be converted to high value-added aromatic compounds and aromatic-derived compounds, and ethylene glycol, which is another monomer of polyethylene terephthalate, can be converted to glycolic acid, which is a cosmetic material. The present invention is characterized by recycling polyethylene terephthalate waste into high value-added compounds.
    Type: Application
    Filed: April 8, 2020
    Publication date: June 9, 2022
    Applicants: Korea University Research and Business Foundation, EWHA UNIVERSITY - INDUSTRY COLLABORATION FOUNDATION
    Inventors: Kyoung Heon KIM, Jeong Chan JOO, Hee Taek KIM, Si Jae PARK, Hyun Gil CHA, Bong Keun SONG, Jae Kyun KIM
  • Publication number: 20210114437
    Abstract: An air conditioning system provides inside air conditioning and performs the function of cleaning the inside air, so that the inside air is maintained to be pleasant. The air cleaning time of cleaning the inside air is decreased, so the possibility of moisture generated on an inside window due to the air cleaning is reduced.
    Type: Application
    Filed: March 19, 2020
    Publication date: April 22, 2021
    Applicants: HYUNDAI MOTOR COMPANY, KIA MOTORS CORPORATION, Hanon Systems
    Inventors: Dong Ho Kwon, Dae Ig Jung, Gee Young Shin, Seung Hyeok Chang, Seong Seok Han, Soo Byeong Nam, Jae Kyun Kim
  • Patent number: 10607248
    Abstract: The present invention relates generally to a method where the price of a commodity open for sale decreases from the seller-entered preset initial price to the seller-entered preset bottom price during the given period of time, and buyers who are willing to buy the commodity may participate in the active price reduction sale. A deal is made once any of the participants selects the price displayed during the market time. The same item that the seller has multiple stock can be marketed altogether, partially or one by one in separate or the same spaces online. Also, the seller can sell multiple different items in the platform using various settings. The deal can be made between commercial retailers, individual sellers or any other entities and buyers online. The commodity may include new or used items, services, tickets, and other items that can be marketable online.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: March 31, 2020
    Inventor: Jae Kyun Kim
  • Publication number: 20180300743
    Abstract: The present invention relates generally to a method where the price of a commodity open for sale decreases from the seller-entered preset initial price to the seller-entered preset bottom price during the given period of time, and buyers who are willing to buy the commodity may participate in the active price reduction sale. A deal is made once any of the participants selects the price displayed during the market time. The same item that the seller has multiple stock can be marketed altogether, partially or one by one in separate or the same spaces online. Also, the seller can sell multiple different items in the platform using various settings. The deal can be made between commercial retailers, individual sellers or any other entities and buyers online. The commodity may include new or used items, services, tickets, and other items that can be marketable online.
    Type: Application
    Filed: April 18, 2017
    Publication date: October 18, 2018
    Inventor: Jae Kyun Kim
  • Patent number: 9583340
    Abstract: Provided are a semipolar nitride semiconductor structure and a method of manufacturing the same. The semipolar nitride semiconductor structure includes a silicon substrate having an Si(11k) surface satisfying 7?k?13; and a nitride semiconductor layer formed on the silicon substrate. The nitride semiconductor layer has a semipolar characteristic in which a polarization field is approximately 0.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: February 28, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun-Youn Kim, Jae-Kyun Kim, Joo-Sung Kim, Young-Soo Park, Young-Jo Tak
  • Patent number: 9422638
    Abstract: Crack formation and propagation in a silicon substrate may be reduced by forming a crack reducing portion. The silicon substrate includes a silicon main portion and a silicon edge portion formed around the silicon main portion. The crack reducing portion is formed on the silicon edge portion of the silicon substrate such that the directions of crystal faces in the crack reducing portion are randomly oriented.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: August 23, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-youn Kim, Jae-Kyun Kim, Su-hee Chae, Hyun-gi Hong
  • Patent number: 9337381
    Abstract: A semiconductor buffer structure includes a silicon substrate, a nucleation layer formed on the silicon substrate, and a buffer layer formed on the nucleation layer. The buffer layer includes a first layer formed of a nitride semiconductor material having a uniform composition rate, a second layer formed of the same material as the nucleation layer on the first layer, and a third layer formed of the same material with the same composition ratio as the first layer on the second layer.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: May 10, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-youn Kim, Young-jo Tak, Jae-kyun Kim, Joo-sung Kim, Young-soo Park, Su-hee Chae
  • Patent number: 9257599
    Abstract: According to example embodiments, a semiconductor light emitting device includes a first semiconductor layer, a pit enlarging layer on the first semiconductor layer, an active layer on the pit enlarging layer, a hole injection layer, and a second semiconductor layer on the hole injection layer. The first semiconductor layer is doped a first conductive type. An upper surface of the pit enlarging layer and side surfaces of the active layer define pits having sloped surfaces on the dislocations. The pits are reverse pyramidal spaces. The hole injection layer is on a top surface of the active layer and the sloped surfaces of the pits. The second semiconductor layer doped a second conductive type that is different than the first conductive type.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: February 9, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-kyun Kim, Joo-sung Kim, Jun-youn Kim, Young-soo Park, Young-jo Tak
  • Patent number: 9202878
    Abstract: A gallium nitride based semiconductor device includes a silicon-based layer doped simultaneously with boron (B) and germanium (Ge) at a relatively high concentration, a buffer layer on the silicon-based layer, and a nitride stack on the buffer layer. A doping concentration of boron (B) and germanium (Ge) may be higher than 1×1019/cm3.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: December 1, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-jo Tak, Jae-kyun Kim, Jun-youn Kim, Jae-won Lee, Hyo-ji Choi
  • Patent number: 9190270
    Abstract: Provided are a low-defect semiconductor device and a method of manufacturing the same. The method includes forming a buffer layer on a silicon substrate, forming an interface control layer on the buffer layer under a first growth condition, and forming a nitride stack on the interface control layer under a second growth condition different from the first growth condition.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: November 17, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-jo Tak, Jae-kyun Kim, Joo-sung Kim, Jun-youn Kim, Young-soo Park, Eun-ha Lee
  • Patent number: 9136430
    Abstract: A method of manufacturing a semiconductor device includes forming a silicon substrate, forming a buffer layer on the silicon substrate, and forming a nitride semiconductor layer on the buffer layer. The buffer layer includes a first layer, a second layer, and a third layer. The first layer includes AlxInyGa1-x-yN (0?x?1, 0?y?1, 0?x+y?1) and has a lattice constant LP1 that is smaller than a lattice constant LP0 of the silicon substrate. The second layer is formed on the first layer, includes AlxInyGa1-x-yN (0?x<1, 0?y<1, 0?x+y<1), and has a lattice constant LP2 that is greater than LP1 and smaller than LP0. The third layer is formed on the second layer, includes AlxInyGa1-x-yN (0?x<1, 0?y<1, 0?x+y<1), and has a lattice constant LP3 that is smaller than LP2.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: September 15, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-jo Tak, Jae-kyun Kim, Joo-sung Kim, Jun-youn Kim, Jae-won Lee, Hyo-ji Choi
  • Publication number: 20150123140
    Abstract: Provided are a semipolar nitride semiconductor structure and a method of manufacturing the same. The semipolar nitride semiconductor structure includes a silicon substrate having an Si(11k) surface satisfying 7?k?13; and a nitride semiconductor layer formed on the silicon substrate. The nitride semiconductor layer has a semipolar characteristic in which a polarization field is approximately 0.
    Type: Application
    Filed: November 4, 2014
    Publication date: May 7, 2015
    Inventors: Jun-Youn KIM, Jae-Kyun KIM, Joo-Sung KIM, Young-Soo PARK, Young-Jo TAK
  • Publication number: 20150111369
    Abstract: A semiconductor buffer structure includes a silicon substrate, a nucleation layer formed on the silicon substrate, and a buffer layer formed on the nucleation layer. The buffer layer includes a first layer formed of a nitride semiconductor material having a uniform composition rate, a second layer formed of the same material as the nucleation layer on the first layer, and a third layer formed of the same material with the same composition ratio as the first layer on the second layer.
    Type: Application
    Filed: September 12, 2014
    Publication date: April 23, 2015
    Inventors: Jun-youn KIM, Young-jo TAK, Jae-kyun KIM, Joo-sung KIM, Young-soo PARK, Su-hee CHAE
  • Publication number: 20150060762
    Abstract: According to example embodiments, a semiconductor light emitting device includes a first semiconductor layer, a pit enlarging layer on the first semiconductor layer, an active layer on the pit enlarging layer, a hole injection layer, and a second semiconductor layer on the hole injection layer. The first semiconductor layer is doped a first conductive type. An upper surface of the pit enlarging layer and side surfaces of the active layer define pits having sloped surfaces on the dislocations. The pits are reverse pyramidal spaces. The hole injection layer is on a top surface of the active layer and the sloped surfaces of the pits. The second semiconductor layer doped a second conductive type that is different than the first conductive type.
    Type: Application
    Filed: May 28, 2014
    Publication date: March 5, 2015
    Inventors: Jae-kyun KIM, Joo-sung KIM, Jun-youn KIM, Young-soo PARK, Young-jo TAK
  • Patent number: 8946773
    Abstract: A semiconductor buffer structure may include a silicon substrate and a buffer layer that is formed on the silicon substrate. The buffer layer may include a first layer, a second layer formed on the first layer, and a third layer formed on the second layer. The first layer may include AlxInyGa1-x-yN (0?x?1, 0?y?1, 0?x+y?1) and have a lattice constant LP1 that is smaller than a lattice constant LP0 of the silicon substrate. The second layer may include AlxInyGa1-x-yN (0?x<1, 0?y<1, 0?x+y<1) and have a lattice constant LP2 that is greater than the lattice constant LP1 and smaller than the lattice constant LP0. The third layer may include AlxInyGa1-x-yN (0?x<1, 0?y<1, 0?x+y<1) and have a lattice constant LP3 that is greater than the lattice constant LP1 and smaller than the lattice constant LP2.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-jo Tak, Jae-kyun Kim, Joo-sung Kim, Jun-youn Kim, Jae-won Lee, Hyo-ji Choi
  • Publication number: 20140353677
    Abstract: Provided are a low-defect semiconductor device and a method of manufacturing the same. The method includes forming a buffer layer on a silicon substrate, forming an interface control layer on the buffer layer under a first growth condition, and forming a nitride stack on the interface control layer under a second growth condition different from the first growth condition.
    Type: Application
    Filed: June 3, 2014
    Publication date: December 4, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-jo TAK, Jae-kyun KIM, Joo-sung KIM, Jun-youn KIM, Young-soo PARK, Eun-ha LEE
  • Publication number: 20140042492
    Abstract: A semiconductor buffer structure may include a silicon substrate and a buffer layer that is formed on the silicon substrate. The buffer layer may include a first layer, a second layer formed on the first layer, and a third layer formed on the second layer. The first layer may include AlxInyGa1-x-yN (0?x?1, 0?y?1, 0?x+y?1) and have a lattice constant LP1 that is smaller than a lattice constant LP0 of the silicon substrate. The second layer may include AlxInyGa1-x-yN (0?x<1, 0?y<1, 0?x+y<1) and have a lattice constant LP2 that is greater than the lattice constant LP1 and smaller than the lattice constant LP0. The third layer may include AlxInyGa1-x-yN (0?x<1, 0?y<1, 0?x+y<1) and have a lattice constant LP3 that is greater than the lattice constant LP1 and smaller than the lattice constant LP2.
    Type: Application
    Filed: March 15, 2013
    Publication date: February 13, 2014
    Inventors: Young-jo TAK, Jae-kyun KIM, Joo-sung KIM, Jun-youn KIM, Jae-won LEE, Hyo-ji CHOI
  • Publication number: 20140045284
    Abstract: A method of manufacturing a semiconductor device includes forming a silicon substrate, forming a buffer layer on the silicon substrate, and forming a nitride semiconductor layer on the buffer layer. The buffer layer includes a first layer, a second layer, and a third layer. The first layer includes AlxInyGa1-x-yN (0?x?1, 0?y?1, 0?x+y?1) and has a lattice constant LP1 that is smaller than a lattice constant LP0 of the silicon substrate. The second layer is formed on the first layer, includes AlxInyGa1-x-yN (0?x<1, 0?y<1, 0?x+y<1), and has a lattice constant LP2 that is greater than LP1 and smaller than LP0. The third layer is formed on the second layer, includes AlxInyGa1-x-yN (0?x<1, 0?y<1, 0?x+y<1), and has a lattice constant LP3 that is smaller than LP2.
    Type: Application
    Filed: August 9, 2013
    Publication date: February 13, 2014
    Inventors: Young-jo TAK, Jae-kyun KIM, Joo-sung KIM, Jun-youn KIM, Jae-won LEE, Hyo-ji CHOI
  • Publication number: 20140014990
    Abstract: Lights-emitting device (LED) packages, and methods of manufacturing the same, include at least one light-emitting structure. The at least one light-emitting structure includes a first compound semiconductor layer, an active layer, and a second compound semiconductor layer that are sequentially stacked, at least one first metal layer connected to the first compound semiconductor layer, a second metal layer connected to the second compound semiconductor layer, a substrate having a conductive bonding layer on a first surface of the substrate, and a bonding metal layer configured for eutectic bonding between the at least one first metal layer and the conductive bonding layer.
    Type: Application
    Filed: March 15, 2013
    Publication date: January 16, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun-youn KIM, Jae-kyun KIM, Joo-sung KIM, Moon-seung YANG, Su-hee CHAE, Young-jo TAK, Hyun-gi HONG
  • Publication number: 20130334496
    Abstract: A semiconductor device includes a silicon substrate; a nitride nucleation layer disposed on the silicon substrate; at least one superlattice layer disposed on the nitride nucleation layer; and at least one gallium nitride-based semiconductor layer disposed on the superlattice layer. The at least one superlattice layer includes a stack of complex layers, each complex layer including a first layer and a second layer such that each of the complex layers has a plurality of nitride semiconductor layers having different compositions, at least one of the plurality of nitride semiconductor layers having a different thickness based on a location of the at least one nitride semiconductor layer within the stack, and at least one stress control layer having a thickness greater than a critical thickness for pseudomorphic growth.
    Type: Application
    Filed: March 15, 2013
    Publication date: December 19, 2013
    Inventors: Jae-kyun KIM, Jun-youn KIM, Young-jo TAK